Z80195 Просмотр технического описания (PDF) - Zilog

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Z80195

SMART PERIPHERAL CONTROLLERS

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TIMING DIAGRAMS (Continued)

PRELIMINARY

Ø

32

31

/INTI

33

/NMI

Z80185/Z80195

SMART PERIPHERAL CONTROLLES

/M1 [1]

30

/IORQ [1]

/Data IN [1]

39

/MREQ [2]

16

15

/RFSH [2]

41

40

42

35

34

/BUSREQ

35

34

/BUSACK

36

37

38

38

Address

Data /MREQ,

/RD, /WR,

/IORQ

43

[3]

44

/HALT

Notes:

[1] During /INT0 acknowledge cycle

[2] During refresh cycle

[3] Output buffer is off at this point

[4] Refer to Table C, parameter 7

Figure 5. CPU Timing

(/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE mode

HALT mode, SLEEP mode, SYSTEM STOP mode)

DS971850301

7

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