TK75050 Просмотр технического описания (PDF) - Toko America Inc
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TK75050 Datasheet PDF : 12 Pages
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TK75050
APPLICATION INFORMATION (CONT.)
addition to the short-circuit protection, the board also illustrates how to use the IC for driving and protecting a floating
switch.
CIRCUIT SCHEMATIC
Figure 8 shows the circuit schematic. The operation is as follows: U1, a 5-pin PWM IC (TK75001) generates a 30 kHz
square-wave signal, with about 15 V peak-to-peak magnitude and 44% duty ratio. That square-wave signal is connected
to the primary winding of a pulse transformer T1 through a coupling capacitor C9 and a small series resistor R11. A voltage-
doubler comprising C3, C4, D3 and D4 rectifies the transformed square wave appearing across the secondary winding of
the transformer, generating a floating supply voltage of about 12 V for the MOSFET driver IC U2 (TK75050). A drive signal
is derived for U2 from the voltage across the diode D4 with the help of the resistive divider R3 and R2. The output of U2
(pin 3) is connected to the gate of the MOSFET Q1 through a 150 ohm resistor R4 and a parallel diode D5. The current
of the MOSFET switch is sensed by resistor R5. D6 and D7 protect the PGND/CS pin (pin 1) of U2 from excessive voltage;
D8 and D9 prevent the voltages of pins 3 and 1 from swinging below ground by more than 0.3 V. The MOSFET Q1 is
connected to a DC-bus through a small inductor L1. That inductor represents the inductance of a wire connection to a
load, which is at a distance of approximately 1 meter from the MOSFET. By placing a short across jumper JP1, we can
emulate the case when the free-wheeling diode in a buck or boost converter fails. If the inductor L1 is not shorted, a clamp
comprising D10, C6 and R7 limits the drain voltage excursion of Q1 to about 60 V above the bus voltage.
A test loop is provided for clamp-on type current probes to monitor the current in the MOSFET Q1. Test points TP1 through
TP4 are available for measuring the dc bus voltage and the voltage across Q1.
The DC-bus is generated by rectifying the line voltage with a bridge rectifier (in the case of 230 VRMS line) or with a voltage
doubler (in the case of 115 VRMS line, when jumper JP2 is shorted). Alternatively, a DC source of not more than 400 V
can be connected to the line terminals.
Notes: (1) Leave JP2 open if you connect more than 250 V dc voltage to the line terminals, otherwise the excess voltage across C7 or C8 can lead
to failure of the capacitor. (2) Never operate the circuit from 230 VRMS line with the jumper JP2 shorted. In such a case excess bus voltage will develop
that will destroy capacitor C7 and C8 and transistor Q1.
TP4
TEST POINT FOR VOLTAGE OBSERVATION
TEST LOOP
FOR CURRENT
PROBE
JP1
+15 V
TP5
D5
Q1
L1
R10
D11
1k
1N5226B (3.3 V)
R4
HS1 D10
C7
150
R7
C2
1.5 n
FB
CT
GND
GND
VCC
+
C1
DRV
U1
TK75001
D2 C9
C3
1
1
R11
10
n1
n2
D1
T1
D3
R1
10
C5
+ 0.1
C4
D4
U2
TK75050
VCC
GND
IN
D7
Q1: IRF820 (IR PREFERRED)
HS1: HS121-ND (DIGI-KEY, AAVID)
R2
R3
10 k
D1, D2, D5, D8, D9: 1N5817
D3, D4, D6, D7: 1N4148
22 k
D10: BYV26C
D12-15: 1N4005
C1, C4: 10 , 25 V
C6: 15 n, 630 V(e.g. ECQ-E6153KF, PANASONIC)
C7, C8: 2.2 , 250 V (PANASONIC SU SERIES, RADIAL, ECE-A2EU2R2)
L1: 3.3. , 4 A (e.g. R622LY-3R3M, TOKO)
T1: RM5/i, 3E1 (PHILIPS), n1 = 40, n2 = 46, SINGLE LAYER WINDINGS, WIRE SIZE TO FILL THE BOBBIN
MYLAR INSULATION BETWEEN LAYERS, FOR 1 kV BETWEEN PRIMARY AND SECONDARY
JP2: OPEN AT 230 V, SHORTED AT 115 V.
OUT
GND
PGND/CS
D6
D8
R5
0.47
1W
1k
1W
C6
C8
R6
TP3
D9
10
TP1
TP2
TEST POINT FOR
SCOPE GND CLIP
TEST POINTS FOR
VCC MEASUREMENT
(MAX. 400 VDC)
D12
F1
1A SLOW
D15
R9
1M
JP2
R8
1M
D14
115 OR 230
Vrms
D13
FIGURE 8: CIRCUIT SCHEMATIC
Page 10
January 1999 TOKO, Inc.
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