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HIP1020CK-T Просмотр технического описания (PDF) - Intersil

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HIP1020CK-T Datasheet PDF : 6 Pages
1 2 3 4 5 6
HIP1020
Pin Descriptions
PIN
SYMBOL
FUNCTION
DESCRIPTION
1
VCC
Bias Supply
Connect this pin to either a 12V or a 5V source. The HIP1020 detects the bias-voltage level at
pin 1 and decides whether to operate as a voltage-doubler or a voltage-tripler. Consequently,
it is not recommended to operate with bias voltages between 5V (±10%) and 12V (±10%). In
the absence of an enable signal at pin 5, the current into pin 1 is less than 1µA. It is necessary
for voltage to be present at pin 1 prior to applying an enable signal at pin 5.
2
GND
Ground
Connect to the negative rail of the supply that is connected to pin 1.
3
LGATE Gate Driver for the 5V When VCC = 12V, connect this pin to the gate(s) of the 5V and/or 3.3V MOSFETs. When VCC
and/or 3.3V
= 5V, connect this pin to the gate of a 3.3V MOSFET. Upon a rising edge on EN (pin 5), the
MOSFET(s)
voltage on this pin will ramp linearly to ~16V when VCC = 12V and ~12V when VCC = 5V. An
internal dv/dt activated clamp shunts coupled noise to ground preventing unintended turn on at
either output. The internal dv/dt-activated clamp also protects pin 5.
4
HGATE 12V or 5V MOSFET When VCC = 12V, connect this pin to the gate of the 12V MOSFET. When VCC = 5V, connect
Gate Driver
this pin to the gate of the 5V MOSFET. Upon a rising edge on EN (pin 5), the voltage on this
pin will ramp linearly to ~22V when VCC = 12V and ~13V when VCC = 5V.
5
EN
Enable
Connect a TTL or 3.3V logic signal to this pin to control the outputs at pins 3 and 4. A rising
edge on pin 5 initiates the linear voltage ramps at pins 3 and 4. Be sure that the device driving
EN does not enter a high-impedance state when enabling is not desired and that it’s maximum
rise time does not exceed 100µs.
2

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