AD8013A Просмотр технического описания (PDF) - Analog Devices
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AD8013A Datasheet PDF : 12 Pages
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1.5
1.0
G = +2
RL = 150Ω
0.5
0
–0.5
–1.0
VS = +5V
VS = ±5V
–1.5
–2.0
1M
10M
100M
1G
FREQUENCY – Hz
Figure 34. Closed-Loop Gain Matching vs. Frequency
10
G = +2
8
RL = 150Ω
6
4
VS = +5V
2
VS = ±5V
1.0
G = +2
0.5 RL = 150Ω
0
DELAY
–0.5
–1.0
100k
DELAY
MATCHING
1M
10M
FREQUENCY – Hz
VS = ±5V
VS = +5V
100M
Figure 35. Group Delay and Group Delay Matching
vs. Frequency, G = +2, RL = 150 Ω
Disable Mode Operation
Pulling the voltage on any one of the Disable pins about 1.6 V
up from the negative supply will put the corresponding
amplifier into a disabled, powered down, state. In this
condition, the amplifier’s quiescent current drops to about
0.3 mA, its output becomes a high impedance, and there is
a high level of isolation from input to output. In the case of
the gain of two line driver for example, the impedance at the
output node will be about the same as for a 1.6 kΩ resistor
(the feedback plus gain resistors) in parallel with a 12 pF
capacitor and the input to output isolation will be about
66 dB at 5 MHz.
Leaving the Disable pin disconnected (floating) will leave
the corresponding amplifier operational, in the enabled
state. The input impedance of the disable pin is about 40 kΩ
in parallel with a few picofarads. When driven to 0 V, with
the negative supply at –5 V, about 100 µA flows into the
disable pin.
When the disable pins are driven by complementary output
CMOS logic, on a single 5 V supply, the disable and enable
times are about 50 ns. When operated on dual supplies,
level shifting will be required from standard logic outputs to
the Disable pins. Figure 36 shows one possible method
which results in a negligible increase in switching time.
AD8013
VI
+5V
8k
TO DISABLE PIN
4k
10k
–5V
VI HIGH => AMPLIFIER ENABLED
VI LOW => AMPLIFIER DISABLED
Figure 36. Level Shifting to Drive Disable Pins on Dual
Supplies
The AD8013’s input stages include protection from the large
differential input voltages that may be applied when disabled.
Internal clamps limit this voltage to about ±3 V. The high input to
output isolation will be maintained for voltages below this limit.
3:1 Video Multiplexer
Wiring the amplifier outputs together will form a 3:1 mux with
excellent switching behavior. Figure 37 shows a recommended
configuration which results in –0.1 dB bandwidth of 35 MHz
and OFF channel isolation of 60 dB at 10 MHz on ± 5 V
supplies. The time to switch between channels is about 50 ns.
Switching time is virtually unaffected by signal level.
665Ω
845Ω
+VS
VIN1
6
4
84Ω
7
5
1
75Ω
DISABLE 1
VIN2
665Ω
845Ω
13
12
75Ω
14
2
75Ω
84Ω CABLE
VOUT
75Ω
DISABLE 2
665Ω
845Ω
VIN3
DISABLE 3
9
10
75Ω
8
11
3
–VS
84Ω
Figure 37. A Fast Switching 3:1 Video Mux (Supply
Bypassing Not Shown)
500mV
100
90
200ns
10
0%
5V
REV. A
–11–
Figure 38. Channel Switching Characteristic for the
3:1 Mux
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