AD7884ABP Просмотр технического описания (PDF) - Analog Devices

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AD7884ABP

LC2MOS 16-Bit, High-Speed Sampling ADCs

Analog Devices 

AD7884/AD7885 PERFORMANCE

3000

Linearity

The linearity of the AD7884/AD7885 is determined by the

on-chip 16-bit D/A converter. This is a segmented DAC which

is laser trimmed for 16-bit DNL performance to ensure that

2000

there are no missing codes in the ADC transfer function. Figure

13 shows a typical INL plot for the AD7884/AD7885.

2.0

VDD = +5V

VSS = –5V

TA = +25؇C

1000

1.5

AD7884/AD7885

1.0

0.5

0

0

16384

32768

49152

65535

OUTPUT CODE

Figure 13. AD7884/AD7885 Typical Linearity Performance

Noise

In an A/D converter, noise exhibits itself as code uncertainty in

dc applications and as the noise floor (in an FFT, for example)

in ac applications.

In a sampling A/D converter like the AD7884/AD7885, all

information about the analog input appears in the baseband

from dc to 1/2 the sampling frequency. An antialiasing filter will

remove unwanted signals above fS/2 in the input signal but the

converter wideband noise will alias into the baseband. In the

AD7884/AD7885, this noise is made up of sample-and-hold noise

and A/D converter noise. The sample-and-hold section contrib-

utes 51 µV rms and the ADC section contributes 59 µV rms.

These add up to a total rms noise of 78 µV. This is the input

referred noise in the ± 3 V analog input range. When operating

in the ± 5 V input range, the input gain is reduced to –0.6. This

means that the input referred noise is now increased by a factor

of 1.66 to 120 µV rms.

Figure 14 shows a histogram plot for 5000 conversions of a dc

input using the AD7884/AD7885 in the ± 5 V input range. The

analog input was set as close as possible to the center of a code

transition. All codes other than the center code are due to the

ADC noise. In this case, the spread is six codes.

0

(X – 2) (X – 1) (X) (X + 1) (X + 2) (X + 3)

CODE

Figure 14. Histogram of 5000 Conversions of a DC Input

If the noise in the converter is too high for an application, it can

be reduced by oversampling and digital filtering. This involves

sampling the input at higher than the required word rate and

then averaging to arrive at the final result. The very fast con-

version time of the AD7884/AD7885 makes it very suitable

for oversampling. For example, if the required input bandwidth

is 40 kHz, the AD7884/AD7885 could be oversampled by a

factor of 2. This yields a 3 dB improvement in the effective

SNR performance. The noise performance in the ±5 volt input

range is now effectively 85 µV rms and the resultant spread of codes

for 2500 conversions will be four. This is shown in Figure 15.

1500

1000

500

0

(X – 1) (X) (X + 1) (X + 2)

CODE

Figure 15. Histogram of 2500 Conversions of a DC Input

Using a ×2 Oversampling Ratio

REV. D

–11–

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