MX9691L Просмотр технического описания (PDF) - Macronix International
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MX9691L Datasheet PDF : 41 Pages
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MX9691L
External Memory Bus Interface
Symbol
D[15:0]
A[15:0]
No.
Type
33-37,39-41, I/O
55-58,60-63 (CMOS)
3-5,8-11, I/O
22-24,26-31 (CMOS)
PCE#
DCE#
RD#
67
I/O
(TTL)
68
I/O
(TTL)
65
I/O
(TTL)
WR#
NMI#
INT1#
66
I/O
(TTL)
15
I
(CMOS)
14
I/O
(CMOS)
Description
DSP IO/RAM/ROM/FLASH memory array external data bus.
These pins include internal pull- up resistors.
In Free-run mode, these signals are output that used as DSP
IO/RAM/ROM external address. A14-A0 are used for flash
memory array address also. In upgrade mode, these
address are used for ROM address that controlled by
CYH,CYL registers. In ICE-debugging mode,these address
are input, asserted by DSP ICE(external MX93011 DSP).
And the internal DSP is disabled at this time.
These pins include internal pull-up resistors.
In Free-run mode, this signal is output that is used as
external program chip enable. In upgrade mode, this signal
is drived to high. In ICE-debugging mode, this signal is
input, asserted by DSP ICE(external MX93011 DSP). And
the internal DSP is disabled at this time. This pin includes a
bus holder circuit.
In Free-run mode, this signal is output that is used as
external data chip enable. In upgrade mode, this signal is
drived to high. In ICE-debugging mode, this signal is input,
asserted by DSP ICE(external MX93011 DSP). And the
internal DSP is disabled at this time. This pin includes a bus
holder circuit.
In Free-run mode, this signal is output that is used as DSP
IO/RAM/ROM external read. In upgrade mode, this signal is
output and asserted when the data register is read in host
interface. In ICE-debugging mode, this signal is input, as
serted by DSP ICE(external MX93011 DSP). And the
internal DSP is disabled at this time.
This pin includes a bus holder circuit.
In Free-run mode, this signal is output that is used as DSP
IO/RAM/ROM external write. In upgrade mode, this signal is
drived to high. In ICE-debugging mode, this signal is input,
asserted by DSP ICE(external MX93011 DSP). And the
internal DSP is disabled at this time. This pin includes a bus
holder circuit.
Non maskable interrupt pin.
This pin includes an pull-up resistor.
In Free-run mode, this signal is input that is used as
interrupt pin. Interrupt will be internally asserted also when
data transfer done, or command end. In ICE-debugging
mode, this signal is output and asserted when data transfer
done, or command end. This pin includes an pull-up resistor.
P/N:PM0546
REV. 1.1, JUL. 02, 1999
6
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