VES9600 Просмотр технического описания (PDF) - Philips Electronics

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VES9600

Single Chip DVB-T Channel Receiver

Philips Electronics 

Philips Semiconductors

Single Chip DVB-T Channel Receiver

Product specification

VES9600

43

VREFM

VD1

38

VS1

37

VD2

51

VS2

50

VD3

46

VS3

47

VD4

52

VS4

36

SCL

SDA

SADDR[1:0]

SCL_TUN

SDA_TUN

SCL_EEP

62

63

206-207

64

65

66

SDA_EEP

67

EEPADDR[1:0]

EEPSP[1:0]

204-205

202-203

DOWNLOAD_M

4

ODE

3

DSP_BIST

SDI_TCK

194

SDI_TDI

195

SDI_TMS

196

SDI_TDO

197

1999 Sep 01

from the voltage on pin VREF through an on-chip fully-differential

amplifier. The voltage on this pin is nominally equal to CMO + 0.25

volts.

This is the negative voltage reference for the A/D converter. It is

O

derived from the voltage on pin VREF through an on-chip fully-

differential amplifier. The voltage on this pin is nominally equal to

CMO- 0.25 volts.

I Power supply input for the digital switching circuitry (3.3 typ).

I Ground return for the digital switching circuitry.

I Power supply input for the analog clock drivers (3.3V typ).

I Ground return for the analog clock drivers.

I Power supply input for the analog circuits (3.3V typ).

I Ground return for analog circuits.

I

Power supply input that connects to an n-well guard ring that

surrounds the ADC (3.3V typ).

I

Ground return for the well guard ring that surrounds the ADC.

I2C INTERFACES

I

I2C serial clock. Up to 700 kbit/s, in this functional mode, I2C slave

device

I/O

I2C serial data inout, open drain I/O pad Up to 700 kbit/s, in this

functional mode, I2C slave device

SADDR[1:0] are the 2 LSBs of the I2C address of the VES9600. The

I MSBs are internally set to 00010. Therefore the complete I2C address

of the VES9600 is (MSB to LSB): 0,0,0,1,0,SADDR[1], SADDR[0]

O

tuner I2C serial clock signal. Can be connected or not to the master

I2C bus. (open drain)

I/O

Tuner I2C data bus. Can be connected or not to the master I2C bus.

(open drain)

O

Extra I2C clock line to download DSP code from an external

EEPROM. Optional mode. Can be connected to the master I2C Bus

, (open drain)

I/O Extra I2C data bus to download DSP code from an external EEPROM.

Optional mode. Can be connected to the master I2C Bus. (open drain)

EEPRAD[1:0] are the 2 LSBs of the I2C address of the EEPROM in

I

mode boot alone. The MSBs are internally set to 00010. Therefore the

complete I2C address of the EEPROM is (MSB to LSB):

1,0,1,0,0,EEPADDR[1], EEPADDR[0]

I

I2C EEPROM bus speed (SCL_EEP) :

0 : 800Khz; 1 : 400Khz; 2 : 200Khz; 3 : 100Khz.

DSP SIGNALS

I

processor control, Boot Mode

If 0 the DSP download its software from an external eeprom on the

dedicated I2C BUS SDA_EEP and SCL_EEP.

If 1 the software is downloaded via a host in the I2C register

CODE_IN. In this case no need of an external eeprom.

Boot on the bist mode to test the DSP RAM bank.

I

If good SP_OUT[0] = 1

In normal mode of operation, DSP_BIST must be grounded.

I

Oak+ DSP smart debug interface, SDI+ external JTAG clock

I

Oak+ DSP smart debug interface, SDI+ JTAG serial output

I

Oak+ DSP smart debug interface, SDI+ JTAG test mode select

O

Oak+ DSP smart debug interface, SDI+ JTAG serial output

6

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