VES1820X Просмотр технического описания (PDF) - Philips Electronics

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VES1820X

Single chip DVB-C channel receiver

Philips Electronics 

Philips Semiconductors

Single chip DVB-C channel receiver

Product specification

VES1820X

Next, the RAM memory associated with the deinterleaver fills up and the first deinterleaved bytes are provided to

the input of the Reed-Solomon decoder. The state machine of the de-interleaver goes to the control phase which

counts β consecutive missed MPEG2 sync words (or sync ) before declaring the system desynchronized and

going back to the synchronization phase. α and β are programmable through the I2C interface.

When the inverted sync word is detected at the input of the de-interleaver, the bytes provided to the Reed-

Solomon decoder are inverted at the output of the deinterleaver.

½ REED-SOLOMON DECODER

The Reed-Solomon decoder decodes the symbol stream from the de-interleaver according to the (204, 188)

shortened Reed-Solomon code. Synchronization to Reed-Solomon code is defined over the finite Galois field GF

(28). The field generator polynomial is given by :

p15

G(x) =

(x + a i )

i= 0

This Reed-Solomon decoder corrects up to eight erroneous symbols in each block. When the correction

capability of the decoder is exceeded, the block is not changed and is provided as it has been entered. In this

case the flag UNCOR is set and the MSB of the second byte in the MPEG2 frame is forced to one (error

indicator). The correction capability of the RS decoder can be inhibited.

½ DESCRAMBLER

In order to comply with energy dispersal requirements of radio transmission regulations and to ensure adequate

binary transitions, the MPEG2 frames are scrambled at the encoder side. Dual operation is achieved at the

output of the Reed-Solomon decoder using the same scrambler/descrambler. The polynomial for the pseudo

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15

random binary sequence (PRBS generator is 1 + x + x . The PRBS registers are initialized at the start of every

eight transport packets. To provide an initialization signal for the descrambler, the MPEG2 sync byte of the first

transport packet is inverted from 47 to B8 . When detected, the descrambler is loaded with the initial sequence

16

16

"100101010000000". The descrambler can be inhibited.

½ INTERFACE

The VES1820X integrates an I2C interface in slave mode. This I2C interface fulfills the Philips component I2C

bus specification.

1999 March 01

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