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HFBR-4663

Single Chip 10BASE-FL Transceiver

HP => Agilent Technologies 

The comparator is a high-speed

differential zero crossing detector

that slices and accurately digitizes

the receive signal. The output of

the comparator is fed in parallel

into both the receive squelch

circuit and the loopback MUX.

Link Detect Circuitry and

Low Light

The link detect circuit monitors

the input signal and determines

when the input falls below a

preset voltage level. When the

input falls below a preset voltage,

the HFBR-4663 goes into the Low

Light state. In the Low Light state

the transmitter is disabled, but

continues sending the I MHz idle

signal, the loopback is disabled,

the receiver is disabled and the

LMON LED pin goes to high

shutting off the LMON LED. To

return to the Link Pass state, the

optical receiver power must be

20% higher than the shut-off

state. This built-in hysteresis adds

stability to the Link Monitor

circuit. Once the receiver power

threshold is exceeded, the HFBR-

4663 waits 250 ms to 750 ms,

then checks to see that Tx+, Tx-

is idle and no data is being

received before re-enabling the

transmitter, receiver, loopback

circuit, and lighting up the LMON

LED.

The VTHADJ pin is used to adjust

the sensitivity of the receiver. The

HFBR-4663 is capable of

exceeding the 10BASE-FL

specifications for sensitivity. The

sensitivity is dependent on the

layout of the PC board. A good

low noise layout will exceed the

10BASE-FL specifications, while a

poor layout will fail to meet the

sensitivity and BER spec.

The threshold generator shifts the

reference voltage at VTHADJ

through a circuit which has a

temperature coefficient matching

that of the limiting amplifier. The

relationship between the VTHADJ

and the VTH (the peak to peak

input threshold) is:

VTHADJ = 408 VTH (2)

In a 10BASE-FL receiver, there

must be less than 1 x 10-9 bit

errors at a receive power level of -

32.5 dBm average. One procedure

to determine the sensitivity of a

receiver is to start at the lowest

optical power level and gradually

increase the optical power until

the BER is met. In this case the

Link Detect circuit must not

disable the receiver (i.e. VTHADJ

should be tied to Ground). Once

the sensitivity of the receiver is

determined, VTHADJ can be set just

above the power level that meets

the BER specification. This way

the receiver will shut-off before

the BER is exceeded.

For 10-BASE-FL, VTHADJ can be

tied directly to VREF. However if

greater sensitivity is required the

circuit in Figure 5 can be used to

adjust the VTHADJ voltage. Even if

VREF is tied to VTHADJ, it is a good

idea to layout a board with these

two resistors available. This will

allow potential future adjustments

without board revisions.

The response time of the Link

Detect circuit is set by the CTIMER

pin. Starting from the link off

state the link can be switched on

if the input exceeds the set

threshold for a time given by:

CTIMER x 0.7 V

T= ––––––––––––

700 µA

VREF

R1

VTHADJ

R2

REF

THRESH

GEN

Figure 5.

To switch the link from on to off,

the above time will be doubled. A

value of 0.05 µF will meet the

10BASE-FL specifications.

Differences between

10BASE-FL and FOIRL

10BASE-FL is an improved

version of the original FOIRL

standard. The 10BASE-FL

standard allows backward

compatibility of a 10BASE-FL

transceiver with a FOIRL

transceiver. The main improve-

ments incorporated into 10BASE-

FL are that it can attach to a DTE

by adding the SQE test, and the

distance has been increased from

1 km to 2 km. The other

differences are much more subtle.

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