HI1-0548-5 Просмотр технического описания (PDF) - Intersil
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HI1-0548-5 Datasheet PDF : 24 Pages
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HI-546, HI-547, HI-548, HI-549
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V
Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V
or 20mA, Whichever Occurs First
Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max) . . 40mA
Operating Conditions
Temperature Ranges
HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
16 Ld CERDIP Package . . . . . . . . . . .
85
32
28 Ld CERDIP Package . . . . . . . . . . .
55
18
28 Ld PDIP Package*. . . . . . . . . . . . .
60
N/A
16 Ld PDIP Package . . . . . . . . . . . . .
90
N/A
28 Ld PLCC Package . . . . . . . . . . . . .
70
N/A
20 Ld PLCC Package . . . . . . . . . . . . .
80
N/A
28 Ld SOIC Package . . . . . . . . . . . . .
75
N/A
16 Ld SOIC Package . . . . . . . . . . . . . 105
N/A
Maximum Junction Temperature
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(PLCC, SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless
Otherwise Specified. For Test Conditions, Consult Test Circuits Section
PARAMETER
TEST
TEMP
CONDITIONS
(oC)
MIN
-2
TYP MAX
-5, -9
MIN
TYP MAX UNITS
SWITCHING CHARACTERISTICS
Access Time, tA
25
-
0.5
-
-
0.5
-
µs
Full
-
-
1.0
-
-
1.0
µs
Break-Before Make Delay, tOPEN
Enable Delay (ON), tON(EN)
25
25
80
-
25
80
-
ns
25
-
300
500
-
300
-
ns
Full
-
-
1000
-
-
1000
ns
Enable Delay (OFF), tOFF(EN)
25
-
300
500
-
300
-
ns
Full
-
-
1000
-
-
1000
ns
Settling Time
To 0.1%
25
-
1.2
-
-
1.2
-
µs
To 0.01%
25
-
3.5
-
-
3.5
-
µs
Off Isolation
Note 6
25
50
68
-
50
68
-
dB
Channel Input Capacitance, CS(OFF)
Channel Output Capacitance CD(OFF)
HI-546
25
-
10
-
25
-
52
-
-
10
-
pF
-
52
-
pF
HI-547
25
-
30
-
-
30
-
pF
HI-548
25
-
25
-
-
25
-
pF
HI-549
25
-
12
-
-
12
-
pF
Input to Output Capacitance, CDS(OFF)
DIGITAL INPUT CHARACTERISTICS
25
-
0.1
-
-
0.1
-
pF
Input Low Threshold, TTL Drive, VAL
Input High Threshold, VAH (Note 8)
MOS Drive, VAL (HI-546/547 Only)
VREF = 10V
Full
-
-
0.8
-
-
0.8
V
Full
4.0
-
-
4.0
-
-
V
25
-
-
0.8
-
-
0.8
V
8
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