M5-512/192-7HI/1 Просмотр технического описания (PDF) - Lattice Semiconductor

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M5-512/192-7HI/1

Fifth Generation MACH Architecture

Lattice Semiconductor 

MACH 5 TIMING MODEL

The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5

device, and at the same time, be easy to understand. This model accurately describes all

combinatorial and registered paths through the device, making a distinction between internal

feedback and external feedback. A signal uses internal feedback when it is fed back into the switch

matrix or block without having to go through the output buffer. The input register specifications

are also reported as internal feedback. When a signal is fed back into the switch matrix after having

gone through the output buffer, it is using external feedback.

The parameter, tBUF, is defined as the time it takes to go through the output buffer to the I/O pad.

If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is

followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived.

For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 5 timing model is

shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design

for a more detailed discussion about the timing parameters.

(External Feedback)

(Internal Feedback)

COMB/DFF/

LATCH

IN

tS (S/A)

tPDi

tSLW

OUT

tH (S/A)

tCO (S/A) i Q

tBUF

tSAL

tPDLi

tHAL

tGOAi

INPUT REG/

INPUT LATCH

tSIR (S/A) tCO (S/A) i Q

tBLK

tSEG

tPL1

tPL2

tPL3

tSRR

tSRi

tPT

tCES

tCEH

tHIR (S/A)

tSIL

tPDILi

tGOAi

tEA

CE

SR

tER

tHIL

tSRi

tSRR

tCES

tCEH

CE

SR

PIN CLK

Figure 7. MACH 5 Timing Model

20446G-014

MACH 5 Family

9

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