PC928 Просмотр технического описания (PDF) - Sharp Electronics
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PC928 Datasheet PDF : 10 Pages
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PC928
s Electro-optical Characteristics (2)
(Ta=Topr unless otherwise specified)
Parameter
Symbol
Conditions
MIN. TYP. MAX. Unit Test circuit
*9
*10 Overcurrent detecting voltage
Overcurrent detecting voltage
hysteresis width
VCTH
VCHIS
Ta = 25˚C, IF = 10mA
VCC - VCC - VCC -
V
VCC = VO1 = 24V, RG = 47Ω
6.5 6.0 5.5
CG = 3 000pF, FS = OPEN
1
2
3
V
(9)
*9
O2 "High→Low" delay time
at protection from overcurrent
tPCOHL
Ta = 25˚C
-
4
10
µs
O2 fall time at protection
from overcurrent
VCC = VO1 = 24V, IF = 10mA
(13)
tPCOtf
CG = 3 000pF, RG = 47Ω
2
5
-
µs
CP = 1 000pF, RC = 1kΩ
O2 output voltage at protection
from overcurrent
VOE
FS = OPEN
-
-
2
V (10)
*9
Low level error
signal voltage
Ta = 25˚C, IF = 10mA, IFS = 10mA
VFSL
VCC = VO1 = 24V, RG = 47Ω , CG = 3 000pF, -
0.2 0.4
V
(11)
C = OPEN
High level error
signal current
Error signal "High→Low"
delay time
Error signal output pulse width
IFSH
tPCFHL
∆ tFS
Ta = 25˚C, IF = 10mA, VFS = 24V,
VCC = VO1 = 24V, RG = 47Ω , CG = 3 000pF, -
VC = 0V
Ta = 25˚C, RFS = 1.8kΩ
-
VCC = VO1 = 24V, IF = 10mA
CG = 3 000pF, RG = 47Ω
CP = 1 000pF, RC = 1kΩ
20
-
100 µ A (12)
1
5
µs
(14)
35
-
µs
*9 When measuring overcurrent, protective output and error signal output characteristics, connect a bypass capacitor (0.01 µ F or more) between VCC 13 and GND 14 near the device.
*10 VCTH represents C-terminal voltage when O2output goes from "High" to "Low".
Precautions for Operation
1. It is recommended that a capacitor of about 1000pF is added between C-terminal and GND in order to prevent
malfunction of C-terminal due to noise. In the case of capacitor added, rise of the detecting voltage is delayed.
Thus, use together a resistance of about 1k Ω set between Vcc and C-terminal.
The C-terminal rise time varies with the time constant of CR added. Make it clear before use.
2. The light-detecting element used for this product is provided with a parasitic diode between each terminal and GND.
When a terminal happens to reach electric potential lower than GND potential even in a moment, malfunction
or rupture may result. Design the circuit so that each terminal will be kept at electric potential lower than the
GND potential at all times.
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