LXT305A Просмотр технического описания (PDF) - LevelOne

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LXT305A

Integrated T1/E1 Short-Haul Transceiver wtih Transmit JA

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The LXT305A receives the signal input from one twisted-

pair line on each side of a center-grounded transformer.

Positive pulses are received at RTIP and negative pulses

are received at RRING. Recovered data is output at RPOS

and RNEG, and the recovered clock is output at RCLK.

Refer to Test Specifications for LXT305A receiver timing.

The signal received at RPOS and RNEG is processed

through the peak detector and data slicers. The peak detec-

tor samples the inputs and determines the maximum value

of the received signal. A percentage of the peak value is

provided to the data slicers as a threshold level to ensure

optimum signal-to-noise ratio. For T1 applications (deter-

mined by Equalizer Control inputs EC1 - EC3 ≠ 000 or

001) the threshold is set to 70% of the peak value. This

threshold is maintained above 65% for up to 15 successive

zeros over the range of specified operating conditions. For

E1 applications (EC inputs = 000 or 001) the threshold is

50%.

The receiver is capable of accurately recovering signals

with up to -13.6 dB of attenuation (from 2.4 V), corre-

sponding to a received signal level of approximately 500

mV. Maximum line length is 1500 feet of ABAM cable

(approximately 6 dB of attenuation). Regardless of re-

ceived signal level, the peak detectors are held above a

minimum level of .3 V to provide immunity from impul-

sive noise.

After processing through the data slicers, the received sig-

nal is routed to the data and clock recovery sections, and to

the receive monitor. The data and clock recovery circuits

are highly tolerant with an input jitter tolerance significant-

ly better than required by Pub 62411. Refer to Test Speci-

fications for additional information.

The receiver monitor loads a digital counter at the RCLK

frequency. The count is incremented each time a zero is

received, and reset to zero each time a one (mark) is

received. Upon receipt of 175 consecutive zeros the LOS

pin goes High, and a smooth transition replaces the RCLK

output with the MCLK. Received marks are output regard-

less of the LOS status, but the LOS pin will not reset until

the ones density reaches 12.5%. This level is based on

receipt of at least 4 ones in any 32-bit period with no more

than 15 consecutive zeros.

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