ADSP-21061 Просмотр технического описания (PDF) - Analog Devices

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ADSP-21061

Commercial Grade SHARC DSP Microcomputer

Analog Devices 

ADSP-21061/ADSP-21061L

ADSP-21061 #6

ADSP-21061 #5

ADSP-21061 #4

ADSP-21061 #3

CLKIN

RESET

ADDR31–0

DATA47–0

RPBA

3

ID2–0

011

CONTROL

BR1–2, BR4–6 5

BR3

ADSP-21061 #2

CLKIN ADDR31–0

RESET DATA47–0

RPBA

3

ID2–0

010

CONTROL

CPA

BR1, BR3–6 5

BR2

ADSP-21061 #1

CLKIN

RESET

ADDR31–0

DATA47–0

RPBA

RDx

WRx

3

ID2–0

ACK

MS3–0

001

BUS

PRIORITY

RESET

CLOCK

BMS

PAGE

SBTS

CS

HBR

HBG

REDY

CPA

BR2–6 5

BR1

ADDR

DATA

OE

WE

ACK

CS

CS

ADDR

DATA

GLOBAL MEMORY

AND

PERIPHERAL (OPTIONAL)

BOOT EPROM (OPTIONAL)

ADDR

DATA

HOST PROCESSOR

INTERFACE (OPTIONAL)

Figure 3. Shared Memory Multiprocessing System

DMA transfers can occur between the ADSP-21061’s internal

memory and either external memory, external peripherals, or a

host processor. DMA transfers can also occur between the

ADSP-21061’s internal memory and its serial ports.

DMA transfers between external memory and external periph-

eral devices are another option. External bus packing to 16-,

32-, or 48-bit words is performed during DMA transfers.

Rev. D | Page 5 of 52 | May 2013

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