ADSP-21061 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
ADSP-21061 Datasheet PDF : 52 Pages
| |||
GENERAL DESCRIPTION
The ADSP-21061 SHARC—Super Harvard Architecture Com-
puter—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21061
SHARC is a 32-bit processor optimized for high performance
DSP applications. The ADSP-21061 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dual-
ported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time and operates at
50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table 1 shows perfor-
mance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC represents a new standard of integra-
tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea-
tures including 1M bit SRAM memory, a host processor
interface, a DMA controller, serial ports, and parallel bus con-
nectivity for glueless DSP multiprocessing.
Table 1. Benchmarks (at 50 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4,
with reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
Speed
.37 ms
Cycles
18,221
20 ns
1
80 ns
4
120 ns
6
180 ns
9
300M bps
The ADSP-21061 continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram on Page 1, illustrates the following architec-
tural features:
• Computation units (ALU, multiplier, and shifter) with a
shared data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Interval timer
• On-chip SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and multiprocessor interface
• DMA controller
ADSP-21061/ADSP-21061L
• Serial ports
• JTAG test access port
1 ϫ CLOCK
TO GND
3
4
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
ADSP-21061
CLKIN
EBOOT
LBOOT
IRQ2–0
FLAG3–0
TIMEXP
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
BMS
ADDR31–0
DATA47–0
RD
WR
ACK
MS3–0
PAGE
SW
SBTS
ADRCLK
DMAR1–2
DMAG1–2
CS
HBR
HBG
REDY
RPBA
ID2–0
RESET
BR1–6
CPA
JTAG
7
CS
BOOT
ADDR EPROM
DATA (OPTIONAL)
ADDR
DATA MEMORY-
OE
MAPPED
DEVICES
WE (OPTIONAL)
ACK
CS
DMA DEVICE
(OPTIONAL)
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
Figure 2. ADSP-21061/ADSP-21061L System Sample Configuration
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 processors
are code- and function-compatible with the ADSP-21020,
ADSP-21060, and ADSP-21062 SHARC processors.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier oper-
ations. These computation units support IEEE 32-bit single-
precision floating-point, extended-precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for stor-
ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Rev. D | Page 3 of 52 | May 2013
Share Link: 