ML6510 Просмотр технического описания (PDF) - Micro Linear Corporation
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ML6510 Datasheet PDF : 18 Pages
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ML6510
ECL INPUT BUFFER
CLKINH
1
CLKINL
TTL TO ECL
0
CS BIT
÷(M + 1)
[÷1 TO 64]
PHASE
DETECTOR
÷(N + 1)
[÷1 TO ÷128]
LOOP
FILTER
VCO
80-160 MHz
÷2R
MAXIMUM
DELAY
RCLKH
RCLKL
1
0
CM BIT
0
1
TEST
Figure 3. ML6510 Clock Generation Block Diagram.
SYS_CLK
TO DESKEW BUFFERS
input clock and output clocks. It can thus generate a 2x or
4x or 0.5x frequency multiplication or division from input
to output (e.g. 33 MHz input, 66 MHz output or 66 MHz
input, 33 MHz output, etc.). It also can generate a 1x
frequency output. The VCO frequency is defined by:
( ) N + 1 × 2R
( ) fVCO
=
fREF
×
M+1
and the output frequency is still given by:
fOUT = fVCO/2R
R1
R0 INPUT/OUTPUT RANGE
0
0 80-130 MHz
0
1 40–80 MHz
1
0 20–40 MHz
1
1 10–20 MHz
Note: R implies R1, R0; for -80 version, Not valid: Defaults to R = 01
The VCO still must remain in the range 80–160 MHz, and
the minimum phase detector input frequency is 625kHz =
(80 MHz/128). Thus the product of (N + 1) and 2R should
be limited to 128:
(N + 1) x 2R ≤ 128
to make sure that the
phase detector inputs
remain above the minimum
frequency.
Example: Generating a 2x clock input frequency = 33 MHz
Set R = 01 (output range 40 – 80 MHz), N = 5 (0000101),
M = 2 (000010), M/S = 0
( ( ) ) fVCO
=
fREF
×
N
+ 1 × 2R
M+1
=
33MHz
×
6
× 21
3
=
132MHz
fOUT = fVCO/2R = 132 MHz/21 = 66 MHz
Example: Generating a 1x clock Input frequency = 66 MHz
Set R = 01 (output range 40–80 MHz), set M = 0
(000000), N = 0 (0000000), M/S = 0
fVCO
=
66MHz
×
1× 21
1
=
132MHz
fOUT = fVCO/2R = 132 MHz/21 = 66 MHz
For doing frequency multiplication and division, keep
M ≥ 2 and N ≥ 2 for the lowest skew between input
clock and output clock. Several configurations for doing
frequency multiplication and division are included in the
8 configurations stored in the on-chip ROM (see
PROGRAMMING the ML6510).
9
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