TC520ACPD Просмотр технического описания (PDF) - TelCom Semiconductor Inc => Microchip

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TC520ACPD

SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY

TelCom Semiconductor Inc => Microchip 

SERIAL INTERFACE ADAPTER FOR

TC500 A/D CONVERTER FAMILY

1

TC520A

DETAILED DESCRIPTION

The TC520A input and output signals are outlined in the

table below.

2

PIN DESCRIPTIONS

Pin No.

Pin No.

14-Pin PDIP 16-Pin SOIC

Package Package

1

1

2

2

3

3

Symbol

VDD

DGND

CMPTR

4

4

B

5

5

A

6

6

OSCOUT

7

7

OSCIN

8

N/C

9

N/C

8

10

READ

9

11

DOUT

10

12

DCLK

Description

Input. +5V ±10% power supply input with respect to DGND.

Input. Digital Ground.

Input, active high or low (depending on polarity of the voltage input to A/D

converter). This pin connects directly to the zero-crossing comparator output

(CMPTR) of the TC5xx A/D converter. A High-to-Low state change on this pin

causes the TC520A to terminate the de-integrate phase of conversion.

Output, active high. The A and B outputs of the TC520A connect directly to the

A and B inputs of the TC5xx A/D converter connected to the TC520A. The

binary code on A, B determines the conversion phase of the TC5xx A/D

converter: (A, B) = 01 places the TC5xx A/D converter into the Auto Zero

phase; (A, B) =10 for Integrate phase (INT); (A, B) =11 for De-integrate phase

(DINT) and (A, B) = 00 for Integrator Zero phase (IZ). Please see the TC500

family data sheets for a complete description of these phases of operation.

Output, active high. See pin 4 description above.

Input. This pin connects to one side of an AT-cut crystal having a effective

series resistance of 100Ω (typ) and a parallel capacitance of 20pF (typ). If an

external frequency source is used to clock the TC520A, this pin must be left

floating.

Input. This pin connects to the other side of the crystal described in pin 6

above. The TC520A may also be clocked from an external frequency source

connected to this pin. The external frequency source must be a pulse train

having a duty cycle of 30% (minimum); rise and fall times of 15nsec and a min/

max amplitude of 0 to VIH. If an external frequency source is used, pin 6 must

be left floating. A maximum operating frequency of 4MHz (crystal) or 6MHz

(external clock source) is permitted.

No connection on 16 pin package version.

No connection on 16 pin package version.

Input, active low, level and negative edge triggered. A high-to low transition on

READ loads serial port output shift register with the most recent converted

data. Data is loaded such that the first bit transmitted from the TC520A to the

processor is the overrange bit (OVR), followed by the polarity bit (POL) (high =

input positive; low = input negative). This is followed by a 16 bit data word

(MSB first). (OVR is available at the DOUT as soon as READ is brought low.

This bit may be used as the 17th data bit if so desired.) The DOUT pin of the

serial port is enabled only when READ is held low. Otherwise, DOUT remains in

a high impedance state. A serial port read access cycle is terminated at any

time by bringing READ high.

Output, logic level. Serial port output pin. This pin is enabled only when READ

is low (see READ pin description).

Input, positive and negative edge triggered. Serial port clock. With READ low,

serial data is clocked into the TC520A at each low-to-high transition of DCLK,

and clocked out of the TC520A on each high-to-low transition of DCLK. A

maximum serial port DCLK frequency of 3MHz is permitted.

3

4

5

6

7

8

TELCOM SEMICONDUCTOR, INC.

3-41

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