LTC1596-1ACN Просмотр технического описания (PDF) - Linear Technology
Номер в каталоге
Компоненты Описание
производитель
LTC1596-1ACN Datasheet PDF : 12 Pages
| |||
LTC1595/LTC1596/LTC1596-1
APPLICATIONS INFORMATION
Description
The LTC1595/LTC1596 are 16-bit multiplying DACs which
have serial inputs and current outputs. They use precision
R/2R technology to provide exceptional linearity and
stability. The devices operate from a single 5V supply and
provide ±10V reference input and voltage output ranges
when used with an external op amp. These devices have
a proprietary deglitcher that reduces glitch impulse to
1nV-s over a 0V to 10V output range.
Serial I/O
The LTC1595/LTC1596 have SPI/MICROWIRE compat-
ible serial ports that accept 16-bit serial words. Data is
accepted MSB first and loaded with a load pin.
The 8-pin LTC1595 has a 3-wire interface. Data is shifted
into the SRI data input on the rising edge of the CLK pin.
At the end of the data transfer, data is loaded into the DAC
register by pulling the LD pin low (see LTC1595 Timing
Diagram).
VREF
–10V TO 10V 5V
The 16-pin LTC1596 can operate in identical fashion to the
LTC1595 but offers additional pins for flexibility. Four
clock pins are available STB1, STB2, STB3 and STB4.
STB1, STB2 and STB4 operate like the CLK pin of the
LTC1595, capturing data on their rising edges. STB3
captures data on its falling edge (see Truth Table 1).
The LTC1596 has two load pins, LD1 and LD2. To load
data, both pins must be taken low. If one of the pins is
grounded, the other pin will operate identically to LTC1595’s
LD pin. An asynchronous clear input (CLR) resets the
LTC1596 to zero scale (and the LTC1596-1 to midscale)
when pulled low (see Truth Table 2).
The LTC1596 also has a data output pin SRO that can be
connected to the SRI input of another DAC to daisy-chain
multiple DACs on one 3-wire interface (see LTC1596
Timing Diagram).
Unipolar (2-Quadrant Multiplying) Mode
(VOUT = 0V to –VREF)
The LTC1595/LTC1596 can be used with a single op amp
to provide 2-quadrant multiplying operation as shown in
Figure 1. With a fixed –10V reference, the circuits shown
give a precision unipolar 0V to 10V output swing.
0.1µF
13 14 15 16
10 STB3 CLR VDD VREF RFB
4
STB1
µP
7
SRI
5
LD1
6
LTC1596
SRO
9
LD2
8
STB2
11
STB4
DGND
AGND
TO NEXT DAC
FOR DAISY-CHAINING
12
3
OUT1 1
OUT2
2
33pF
–
LT1001
+
1595/96 F01a
VOUT
0V TO –VREF
5V
VREF
–10V TO 10V
0.1µF 8
12
7 VDD VREF RFB
CLK
µP 6 SRI LTC1595 OUT1 3
5 LD
GND
4
33pF
–
LT1001
+
1595/96 F01b
(b)
VOUT
0V TO –VREF
(a)
Table 1. Unipolar Binary Code Table
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
ANALOG OUTPUT
VOUT
–VREF (65,535/65,536)
–VREF (32,768/65,536) = –VREF/ 2
–VREF (1/65,536)
0V
Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to – VREF
9
Share Link: 