AS1700-NPN Просмотр технического описания (PDF) - Astec Semiconductor => Silicon Link

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AS1700-NPN

Semicustom Bipolar Array

Astec Semiconductor => Silicon Link 

Semicustom Bipolar Array

AS17xx

After testing is complete, make sure that the

breadboard circuit is accurately reflected in the

schematic by doing a thorough check to see if all

modifications to the breadboard are included.

Layout options

After thoroughly testing the breadboard, begin

the layout process. There are three options for

doing the layout:

• Customer layout - You do the layout and

provide Astec with a completed layout sheet

(at 500x - which Astec will provide) ready for

entry into our CAD system. Astec will review

the layout for design rule violations and ad-

vise you so that you can correct them yourself

or elect to have Astec fix them.

• Vendor layout - You may assign Astec the

responsibility of the IC layout.

• Customer supervised layout - You assign

the layout implementation to Astec but retain

the responsibility for the final form and con-

tent. Basically you are subcontracting Astec

to do the IC layout under your direction. This

option requires a great deal of communication

between the customer and Astec, but can

yield the greatest control for the customer

while reducing the layout time.

Layout guidelines

We recommend that several copies of the layout

on the data sheet be made to facilitate the layout

process before working with the 500x layout

sheet. The layout copies can be used to sketch

various interconnect options, and work out any

design problems that may be encountered be-

cause of the layout process.

Functional blocks: We recommend that the

circuit be broken down into functional blocks.

The blocks are selected in such a way as to

minimize the the number of interconnections

with the other blocks. If the blocks are in

sequence, the circuit can usually be divided so

that only one or two connections are made

between the blocks (other than power supply

connections).

Block location: Next, add up the number of

devices and pads required by each block. Then

select an area of the chip for each block. There

are a few considerations which must be kept in

mind for the block placement. First, the selected

area must contain the required number of com-

ponents and pads. Second, the various areas

should be located so that interconnections be-

tween them are as easy as possible. Finally, the

locations of the various pads to be bonded to

pins and their relationships to each other and the

blocks should be considered. Bond wires should

not cross each other.

Cross-unders & buses: Cross-unders can be

useful for small resistance values, but be careful

of connections that can not tolerate cross-under

resistance (see resistor summary), such as the

base connections for a diode-biased current

source, etc. To make sure that a connection can

tolerate the cross-under resistance, insert the

appropriate valued resistor in the breadboard

and evaluate its effect on circuit performance.

Buses have low resistance and are valuable for

connecting functional blocks together, and bus-

ing power supply voltages.

Thermal considerations: If one or more com-

ponents dissipate heat, they should be located

away from other components that require close

matching. The matched components should be

placed together an equal distance from the

thermal source. This way both of the matched

components will be heated equally. Total power

dissipation in the circuit is a function of the

package type and size. On average at least

500 mW can be dissipated without trouble. Larger

packages can dissipate more heat.

ASTEC Semiconductor

129

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