ADP3810AR-12.6 Просмотр технического описания (PDF) - Analog Devices

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ADP3810AR-12.6

Secondary Side, Off-Line Battery Charger Controllers

Analog Devices 

ADP3810/ADP3811

either present or absent. If the battery is present, its large ca-

Step 2. Pick the voltage and current loop crossover frequen-

pacitance creates a very low frequency dominant pole, giving a

cies, fev and fe/:

single pole system. The more demanding case is when the bat- To avoid interference betWeen the voltage loop and the current

tery is removed. Now the output pole is dependent upon the

filter capacitors, CPI and CP2. This pole is higher in frequency,

and more care must be taken to stabilize the loop response. All

loop, use fcv < 1/10 offcl> the current loop crossover. The cur-

- rent loop crossover fCI is chosen to be 1.9 kHz to provide a

- fast current limiting response time, so pick fcv 100 Hz.

three cases are described in detail below.

Step 3. Calculate GMODatfev:

The following calculations for compensation components help

The modulator gain of 46.7 dB is the dc gain. The modulator

to realize stable voltage and current loops. In practical designs, pole reduces this gain above fPM.

checking the stability using a network analyzer or a Feedback

Loop Analyzer is always recommended. The calculated compo-

nent values serve as good starting values for a measurement-

based optimization. The component values shown in Figure 23

2

( )fcv

GMOD(100 Hz)= GMOD(de)-20XIOg,/I+

fpM

are slightly different from the calculated values based on this

optimization procedure.

( ) To simplify the analysis further, the loop gain is split into two

components: the gain from the battery to the ADP3810/

ADP3811's CaMP pin and the gain from the CaMP pin back

= to the battery. Because the compensation of each loop depends

Oupon the RC netWork on the CaMP pin, it is a convenient

choice for dividing the loop calculations.

B Definitions:

= S Modulator Gain:

O Error Amplifier:

Loop Gain:

L Modulator Pole:

GMOD gain in dB from the CaMP pin to

VBAT.

= GEA gain in dB from VBATto the CaMP pin.

= Gwop GMOD + ~.

fPM,The pole present at the output of the

modulator.

E Modulator Zero: fzM, The zero due to the ESR, Rpl' of the

TE filter cap, CFI.

GMOD (100Hz)=48.3dB-20xlog,/I+

2

100

0- .11 =-10.9dB

Step 4. Calculate gain loss of GEAat fcv:

To have the feedback loop gain cross over 0 dB at fCv 100 Hz,

~ (100 Hz) should be +10.9 dB. Thus, the total gain loss of

~ needed at crossover is:

= = = GLOSS GEA (de) - GEA (100 Hz) 48.5 dB - 10.9 dB 37.6 dB

Step 5. Determinefpneeded to achieve GLosS:

To achieve this Choss we need to add a pole, which is located at

the CaMP pin. GM2 has practically no parasitic loss in

gain at 100 Hz. Its first parasitic pole occurs at approximately

500 kHz as shown in Figure II. Thus, the entire gain loss must

be realized with an external compensation capacitor, CCI' that

sets the pole, fpI.

Voltage Loop Compensation, No Battery

fpI , fcv

-1. 3Hz

Step 1. Calculate the dc loop gain (GwOP),fpM' andf2M:

( ) GLOSS

10 10 -I

GMOD=20xlog[GM3xITXoc

xRpxAv2XGM4xR4]

Step 6. Calculate CCI based upon /po'

6 mA / V x 0.36 x 3.3 kQ x

GMOD =20 x log

=48.3 dB

[ 0.333 x 0.091 A / V x 1.2 kQ ]

GEA =20XIOg[ RI~2R2XGM2XR5]

I

Ccl =

",0.3j.LF

2nx R5x fPl

Step 7. Calculate the loop phase margin, <11M:

The loop phase margin is a combination of the phase of the

modulator pole and zero and the error amplifier pole.

20kQ

GEA =20xlog [ 80kQ+20kQ

x2.lmA/Vx400kQ

=48.5dB

]

= = GLOOP 44.5 dB + 48.3 dB 96.8 dB

= fpM

I

-

I

-O.l1Hz

2nxR4x(CPI +CP2) 2nX1.2kQx(1.22mF)

fZM =

I

2nxRplxCPI

I

2nxO.IQx1.0mF

-1.6kHz

In reality, the interaction of CFI and CP2and their ESRs create

an additional pole/zero pair, but because the value of RFI (ESR

of CFI) and RF2(ESR of CP2)are similar, they tend to cancel

each other out. Furthermore, the loop crossover is an order of

magnitude lower in frequency, so the additional pole and zero

have little effect on the loop response.

( ) { ) ( ) «PM=180-aretan -fcv -areta -fcv +aretan -fcv "'0°

fpI

fpM

fZM

Step 8. Calculate RcI to stabilize the loop:

The sum of phase losses of the modulator and error amplifier re-

sults in a loop phase of 0°, which is unacceptable for loop stabil-

ity. To stabilize the feedback loop, we have to add a phase

boosting zero to the error amplifier by inserting a resistor (Rei)

in series with the capacitor CCI. If the desired phase margin is

= <11M 60 degrees, the frequency of the zero can be calculated:

= fzl

!cvltan

= <11M 57 Hz

From this, the Rei resistor is calculated:

I

Rei

=

2nxfzlxCci

",IOkQ

-14-

REV. 0

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