AS2333N Просмотр технического описания (PDF) - Astec Semiconductor => Silicon Link

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AS2333N

Secondary side housekeeping circuit

Astec Semiconductor => Silicon Link 

Secondary Side Housekeeping Circuit

AS23xx

require a specific timing sequence for the POK

signal. Some PSU systems also require an

isolated, low voltage, low power remote turn-on

switch, rather than a large line cord switch.

2.1 VREF Enable of Chip Bias

Since the VCC of the AS23xx comes up in a finite

amount of time, and since the VREF of the chip

and the bias for the comparators are not within

specification until approximately 4.2 V of VCC is

available, the comparators for OV and UV and

most other functions are disabled until VREF is

within spec. This prevents the false detection of

a FAULT due to an erroneous VREF. Similarly,

if VREF is too heavily loaded and gets pulled low

out of spec, these functions will also shut off.

2.2 Blanking UV’s During Start-up: UVB

As the power supply outputs come up, the

undervoltage FAULTs must be blanked to allow

the supply to complete its start-up. Putting a

capacitor to ground on the UVB pin will allow the

PSU designer to set a specific period of time

during which undervoltages will not propogate to

the FAULT pin. The UVB pin provides a 1 µA

current source to charge the cap, and once the

UVB pin charges above 2.5 V, the undervoltage

sensing is enabled. UVB does not blank

undervoltages to the POK pin. The UVB pin is

clamped one diode above VREF, or about 3.1 V,

allowing fast discharge of the capacitor when the

system resets.

2.3 POK Bias

The POK pin has some specific requirements

based on industry standard PC power supply

specifications. At start-up, the POK pin must not

rise above 0.4 V. The POK pin is an NPN open

collector whose base is tied to VCC via a simple

resistor. Therefore, once VCC pulls above one

diode or about 0.6 V, the POK pin will go low and

saturate. If the POK pin external pull-up is to the

5 V output, the POK signal will not go above 0.4

V if the VCC of the AS23xx is tied to the 12 V

output or an auxilliary rail.

2.4 POK Start-up Timing: PGCAP

In addition to 2.3 above, most PC power supplies

require the POK pin to remain low until all outputs

have been good for at least 100 ms but not more

than 500 ms. A cap to ground on the PGCAP pin

allows to the PSU designer to set the timing

delay between the PSU outputs becoming good

and the POK pin going high. The PGCAP pin

provides a 1 µA current source to charge the cap,

and when the cap charges above 2.5 V, the POK

pin goes high. When an undervoltage occurs,

the PGCAP pin discharges rapidly and the POK

pin goes low. The POK pin does not respond to

overvoltages.

2.5 Isolated Remote On/Off Switching: OFF

and FAULT

A low voltage, isolated remote on/off switch may

be implemented with the AS23xx OFF pin. If the

chip VCC is run off an auxilliary rail, the FAULT

signal may be used to start and stop the PSU.

When the OFF pin is pulled from high to low or

grounded, the FAULT pin resets to a low state,

which may be used to drive an optocoupler to

enable the primary side PWM controller. Allow-

ing the OFF pin to go open circuit or high causes

the POK pin to go low immediately, and the

FAULT pin will go high after a time delay set by

a cap to ground on the DELAY pin. This allows

the customer’s system to receive a POK warning

before the PSU actually shuts down.

Section 3 - PSU Shutdown Sequences

3.0 Shutdown Sequence

For normal shutdowns, the primary requirement

is that the POK signal should go low some

minimum time before the PSU outputs fall out of

spec.

ASTEC Semiconductor

99

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