CY7C1018CV33-10VC(2006) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1018CV33-10VC Datasheet PDF : 7 Pages
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CY7C1018CV33
AC Test Loads and Waveforms[4]
3.3V
OUTPUT
30 pF
R 317Ω
R2
351Ω
3.0V
GND
ALL INPUT PULSES
90%
10%
90%
10%
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
(c)
R2
351Ω
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
Switching Characteristics Over the Operating Range[5]
-10
-12
-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE LOW to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[6, 7]
tLZCE
CE LOW to Low-Z[7]
tHZCE
CE HIGH to High-Z[6, 7]
tPU[8]
CE LOW to Power-up
tPD[8]
CE HIGH to Power-down
Write Cycle[9, 10]
0
0
0
ns
5
6
7
ns
3
3
3
ns
5
6
7
ns
0
0
0
ns
10
12
15
ns
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-up to Write End
8
9
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-up to Write End
5
6
8
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low-Z[7]
WE LOW to High-Z[6, 7]
0
0
0
ns
3
3
3
ns
5
6
7
ns
Notes:
4. AC characteristics (except High-Z) for all speeds are tested using the Thèvenin load shown in Figure (a). High-Z characteristics are tested for all speeds using
the test load shown in Figure (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05131 Rev. *D
Page 3 of 7
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