AS5SS128K36 Просмотр технического описания (PDF) - Austin Semiconductor

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AS5SS128K36

128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT

Austin Semiconductor 

Austin Semiconductor, Inc.

SRAM

AS5SS128K36

FUNCTIONAL BLOCK DIAGRAM

17

SA0, SA1, SA

MODE

CLK

CKE\

K

CE

ADDRESS

REGISTER

17

15

17

SA1

SA0

D1

D0

ADV/LD\

K

BURST

LOGIC

SA1'

Q1 SA0'

Q0

17

WRITE ADDRESS

17

REGISTER

ADV/LD\

BWa\

BWb\

BWc\

BWd\

R/W\

OE\

CE\

CE2

CE2\

WRITE REGISTRY AND

DATA COHERENCY

CONTROL LOGIC

READ

LOGIC

O

S

E

N

D

A

T

A

U

T

P

U

T

128K X 9 X 4

S

WRITE

DRIVERS

MEMORY

ARRAY

E

S

T

B

DQs

A

M

P

S

E

E

R

I

N

G

U

F

F

E

R

S

E

INPUT E

REGISTER

NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed

information.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

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