RM5231-150-Q Просмотр технического описания (PDF) - PMC-Sierra

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RM5231-150-Q

Microprocessor with 32-Bit System Bus

PMC-Sierra 

RM5231™ Microprocessor with 32-Bit System Bus Data Sheet

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Table of Contents

Legal Information ...........................................................................................................................2

Revision History .............................................................................................................................3

Document Conventions .................................................................................................................4

Table of Contents ..........................................................................................................................5

List of Figures ................................................................................................................................7

List of Tables .................................................................................................................................8

1 Features ..................................................................................................................................9

2 Block Diagram .......................................................................................................................10

3 Hardware Overview ...............................................................................................................11

3.1 Superscalar Dispatch ...................................................................................................11

3.2 CPU Registers .............................................................................................................11

3.3 Pipeline ........................................................................................................................11

3.4 Integer Unit ..................................................................................................................12

3.5 Register File .................................................................................................................12

3.6 ALU ..............................................................................................................................12

3.7 Integer Multiply/Divide ..................................................................................................12

3.8 Floating-Point Co-Processor ........................................................................................13

3.9 Floating-Point Unit .......................................................................................................13

3.10 Floating-Point General Register File ............................................................................15

3.11 System Control Co-processor (CP0) ............................................................................15

3.12 System Control Co-Processor Registers .....................................................................15

3.13 Virtual to Physical Address Mapping ............................................................................16

3.14 Joint TLB ......................................................................................................................17

3.15 Instruction TLB .............................................................................................................18

3.16 Data TLB ......................................................................................................................18

3.17 Cache Memory .............................................................................................................18

3.18 Instruction Cache .........................................................................................................18

3.19 Data Cache ..................................................................................................................19

3.20 Write Buffer ..................................................................................................................20

3.21 System Interface ..........................................................................................................21

3.22 System Address/Data Bus ...........................................................................................21

3.23 System Command Bus ................................................................................................21

3.24 Handshake Signals ......................................................................................................22

3.25 Non-overlapping System Interface ...............................................................................22

3.26 Enhanced Write Modes ................................................................................................23

3.27 External Requests ........................................................................................................24

3.28 Interrupt Handling ........................................................................................................24

3.29 Standby Mode ..............................................................................................................24

3.30 JTAG Interface .............................................................................................................24

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

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Document ID: PMC-2002165, Issue 1

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