RM5231-200-Q Просмотр технического описания (PDF) - PMC-Sierra

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RM5231-200-Q

Microprocessor with 32-Bit System Bus

PMC-Sierra 

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

Released

Figure 4 CP0 Registers

PageMask

5*

EntryHi

10*

47

EntryLo0

2*

EntryLo1

3*

TLB

(entries protected

from TLBWR)

0

LLAddr

17*

TagLo

28*

TagHi

29*

Index

0*

Random

1*

Wired

6*

PRId

15*

Config

16*

Context

4*

Count

9*

Status

12*

EPC

14*

ECC

26*

BadVAddr

8*

Compare

11*

Cause

13*

XContext

20*

CacheErr

27*

ErrorEPC

30*

Used for memory

management

Used for exception

processing

* Register number

3.13 Virtual to Physical Address Mapping

The RM5231 provides three modes of virtual addressing:

• user mode

• kernel mode

• supervisor mode

This mechanism is available to system software to provide a secure environment for user

processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the

user mode, the RM5231 provides a single, uniform virtual address space of 1TB (2 GB in 32-bit

mode).

When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5 TB (4

GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of

the virtual address.

The RM5231 processors also support a supervisor mode in which the virtual address space over 2

TB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the virtual

address.

When the RM5231 is configured as a 64-bit microprocessor, the virtual address space layout is an

upward compatible extension of the 32-bit virtual address space layout.

Figure 5 shows the address space layout for 32-bit operation.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

16

Document ID: PMC-2002165, Issue 1

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