RM5231-200-Q Просмотр технического описания (PDF) - PMC-Sierra

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RM5231-200-Q

Microprocessor with 32-Bit System Bus

PMC-Sierra 

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

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3.10 Floating-Point General Register File

The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the

floating-point load and store double instructions (LDC1 and SDC1), the floating-point unit can

take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store

doubleword instruction in every cycle.

The floating-point control register space contains two registers; one for determining configuration

and revision information for the coprocessor and one for control and status information. These are

primarily used for diagnostic software, exception handling, state saving and restoring, and control

of rounding modes. To support superscalar operation, the FGR has four read ports and two write

ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports

and one write port are used to support the combined multiply-add instruction while the fourth read

and second write port allows a concurrent floating-point load or store.

3.11 System Control Co-processor (CP0)

The system control co-processor, also called coprocessor 0 or CP0 in the MIPS architecture, is

responsible for the virtual memory sub-system, the exception control system, and the diagnostics

capability of the processor. In the MIPS architecture, the system control co-processor (and thus the

kernel software) is implementation dependent.

The memory management unit controls the virtual memory system page mapping. It consists of an

instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint

instruction and data address translation buffer, JTLB, and co-processor registers used by the virtual

memory mapping sub-system.

3.12 System Control Co-Processor Registers

The RM5231 incorporates all system control co-processor (CP0) registers on-chip. These registers

provide the path through which the virtual memory system’s page mapping is examined and

modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,

interrupts enabled or disabled, cache features). In addition, the RM5231 includes registers to

implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data

error detection.

Figure 4 shows the CP0 registers.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

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Document ID: PMC-2002165, Issue 1

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