HD155121F Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HD155121F

RF Transceiver IC for GSM and PCN Dual band cellular systems

Hitachi -> Renesas Electronics 

HD155121F

Transmitter Operation

The transmitter chain converts differential IQ baseband signals to a suitable format for transmission by a

power amplifier.

The common mode voltage range of the modulator inputs is 0.8 V to 1.2 V and they have 2.0 Vpp

differential swing. The modulator circuit uses double-balanced mixers for the I and Q paths. The Local

signals are generated by dividing the IFLO signals by 2, and then passed to the modulator through a phase

splitter / shifter. The IF signals generated are then summed to produce a single modulated IF signal which

is amplified and fed into the offset PLL block. Carrier suppression due to the mixer circuit is better than 31

dBc. If the common mode DC voltage of the I and Q inputs is adjusted, carrier suppression is better than

40 dBc easily. Side band suppression is better than 35 dBc without adjustment.

Within the offset PLL block there are a down converter, a phase comparator and a VCO driver. The down

converter mixes the first local signal and the TXVCO signal to create a reference local signal for use in the

offset PLL circuit. The phase comparator and the VCO driver generate an error current, which is

proportional to the phase differential between the reference IF and the modulated IF signals. This current is

used in a second order loop filter to generate a voltage, which in turn modulates the TXVCO. In order to

optimize the PLL loop gain, the error current value can be modified by changing the value of an external

resistor - ICURAD. In order to accommodate various control range of TXVCOs, the offset PLL circuit has

been designed to operate with a supply voltage up to 5.25 V.

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