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CY7C1024AV33-12BGC Просмотр технического описания (PDF) - Cypress Semiconductor

Номер в каталоге
Компоненты Описание
производитель
CY7C1024AV33-12BGC
Cypress
Cypress Semiconductor Cypress
CY7C1024AV33-12BGC Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
CY7C1024AV33
Switching Characteristics[5] Over the Operating Range
Parameter
Description[3]
7C1024AV33-10
Min.
Max.
7C1024AV33-12
Min.
Max.
7C1024AV33-15
Min.
Max. Unit
READ CYCLE
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE active to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE active to Low Z[7]
CE inactive to High Z[6, 7]
0
0
0
ns
5
6
6
ns
3
3
3
ns
5
6
6
ns
tPU
CE active to Power-Up
0
0
0
ns
tPD
CE inactive to Power-Down
WRITE CYCLE[8, 9]
10
12
15
ns
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE active to Write End
8
9
9
ns
tAW
Address Set-Up to Write End
7
8
8
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
8
ns
tSD
Data Set-Up to Write End
5
6
6
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
0
0
0
ns
3
3
3
ns
5
6
6
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05149 Rev. *B
Page 5 of 11

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