CY7C1011BV33-12ZI Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1011BV33-12ZI

128K x 16 Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Read Cycle No. 2 (OE Controlled)[10, 11]

ADDRESS

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

CY7C1011BV33

tHZOE

DATA VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

50%

IICCCC

IISSBB

1011B-6

Write Cycle No. 1 (CE Controlled) [12, 13]

ADDRESS

CE

tSA

WE

BHE, BLE

DATA I/O

tWC

tSCE

tAW

tPWE

tBW

tSD

Notes:

11. Address valid prior to or coincident with CE transition LOW.

12. Data I/O is high impedance if OE or BHE and/or BLE= VIH.

13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

tHA

tHD

1011B-7

Document #: 38-05021 Rev. *A

Page 6 of 10

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