CY7C1011BV33-15ZC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1011BV33-15ZC Datasheet PDF : 10 Pages
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CY7C1011BV33
Switching Characteristics[5] Over the Operating Range
Parameter
WRITE CYCLE[8]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Description
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[6, 7]
Byte Enable to End of Write
Switching Waveforms
Read Cycle No. 1[9, 10]
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
1011BV33-12
Min.
Max.
12
10
10
0
0
10
7
0
3
6
10
1011BV33-15
Min.
Max.
15
12
12
0
0
12
8
0
3
7
12
tRC
DATA VALID
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1011B-5
Note:
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
10. WE is HIGH for read cycle.
Document #: 38-05021 Rev. *A
Page 5 of 10
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