SPT9101 Просмотр технического описания (PDF) - Signal Processing Technologies
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SPT9101 Datasheet PDF : 8 Pages
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ELECTRICAL SPECIFICATIONS
+VS=+5.0 V, -VS=-5.2 V, RLOAD=100 Ω, unless otherwise specified.
TEST
PARAMETERS
CONDITIONS
Hold Mode Dynamics
Worst Harmonic
VOut = 2 V p-p
Worst Harmonic
VOut = 2 V p-p
Worst Harmonic
VOut = 2 V p-p
Worst Harmonic
VOut = 2 V p-p
Sampling Bandwidth2
VIN = 0.5 V p-p
Hold Noise3 (RMS)
Droop Rate
Feedthrough Rejection (50 MHz)
VOut = 2 V p-p
Maximum Hold Time, VIN=0 V
23 MHz, 50 MSPS
+25 °C
48 MHz, 100 MSPS
+25 °C
48 MHz, 100 MSPS
Full Temp.
48 MHz, 125 MSPS
+25 °C
-3 dB, +25 ˚C
+25 °C
VIN=0.0 V, +25 °C
Full Temp.
Full Temp.
Track-and-Hold Switching
Aperture Delay
Aperture Jitter
Pedestal Offset, VIN=0 V
Transient Amplitude
Settling Time to 4 mV
Glitch Product4
VIN = 0 V
+25 °C
+25 °C
+25 °C
Full Temp.
VIN = 0 V, Full Temp.
Full Temp.
+25 °C
Hold-to-Track Switching
Acquisition Time to 0.1%
2 V Output Step
Acquisition Time to 0.01%
2 V Output Step
+25 °C
+25 °C
Full Temp.
Power Supply5
+VS Voltage
-VS Voltage
Power Dissipation
Full Temp, Track Mode
Full Temp, Clocked Mode
Full Temp, Track Mode
Full Temp, Clocked Mode
Full Temp, Track Mode
Full Temp, Clocked Mode
TEST
LEVEL
V
IV
IV
V
V
V
V
V
IV
V
V
I
VI
V
V
V
SPT9101
MIN
TYP
MAX UNITS
-75
-62
-57
350
150 x tH
-40
-66
100
200
dB FS
-57 dB FS
-53 dB FS
dB FS
MHz
mV/s
mV/µs
dB
ns
-250
<1
±10
8
4
20
ps
ps rms
±25 mV
±35 mV
mV
ns
pV-s
V
7
ns
IV
11
14 ns
IV
16 ns
VI
54
65 mA
VI
44
55 mA
VI
54
65 mA
VI
44
55 mA
VI
551
663 mW
VI
449
561 mW
1Time to recover within rated error band from 160% overdrive.
2Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the
sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier.
3Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (tH) is 20 ns, the accumulated
noise is typically 3 µV (150 mV/s x 20 ns). This value must be combined with the track mode noise to obtain total noise.
4Total energy of worst case track-to-hold or hold-to-track glitch.
Typical thermal impedances: ΘJC (LCC) = +6 °C/W
ΘJA (SOIC) = +85 °C/W in still air at +25 °C ambient.
5Clocked mode is specified with a 50% clock duty cycle.
6Analog input voltage should be limited ≤0.8 volts to maintain device in linear range.
SPT
3
SPT9101
12/30/99
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