MU9C4480A-12DC Просмотр технического описания (PDF) - Music Semiconductors

Номер в каталоге

Компоненты Описание

производитель

MU9C4480A-12DC

LANCAMs®

Music Semiconductors 

MU9C4480A/L

OPERATIONAL CHARACTERISTICS Continued

CAM Status

Validity bits at all memory locations

Match and Full Flag outputs

IEEE 802.3-802.5 Input Translation

CAM/RAM Partitioning

Comparison Masking

Address register auto-increment or -decrement

Source and Destination Segment counters count ranges

Address register and Next Free Address register

Page Address and Device Select registers

Control register after reset (including CT15)

Persistent Destination for Command writes

Persistent Source for Command reads

Persistent Source and Destination for Data reads and writes

Operating Mode

Configuration Register set

/RESET Condition

Skip = 0, Empty = 1 (empty)

Enabled

Not Translated

64 bits CAM, 0 bits RAM

Disabled

Disabled

00B to 011B; loaded with 00B

Contains all 0s

Contains all 0s (no change on software reset)

Contains 0008H

Instruction decoder

Status register

Comparand register

Standard

Foreground

Table 4: Device Control State after Reset

Table 5a. Standard Mode is identical to the operation of the

original MU9C1480 LANCAM. When operating in Enhanced

mode, it is not necessary to unlock the daisy chain with a NOP

instruction before command or data writes after a non-

matching compare, as required in the Standard mode.

If a sequence of data writes or reads is interrupted, the Segment

Control register can be reset to its initial start limit values by

using an RSC instruction. After the LANCAM is reset, both

Source and Destination counters are set to count from Segment

0 to Segment 3 with an initial value of 0.

Segment Control Register (SC)

Page Address Register (PA)

The Segment Control register, as shown in Table 9 on page The Page Address register is loaded using a TCO PA

21, is accessed using a TCO SC instruction. On read cycles, instruction followed by a Command Write cycle of a user

D15, D10, D5, and D2 will always read back as 0s. Either the selected 16-bit value (not FFFFH). The entry in the PA

Foreground or Background Segment Control register will register is used to give a unique address to the different

be active, depending on which register set has been devices in a daisy chain. In a daisy chain, the PA value of

selected, and only the active Segment Control register will each device is loaded using the SFF instruction to advance

be written to or read from.

to the next device, as shown in the “Setting Page Address

Register Values” section on page 15. A software reset (using

The Segment Control register contains dual independent the Control register) does not affect the Page Address register.

incrementing counters with limits, one for data reads and

one for data writes. These counters control which 16-bit Device Select Register (DS)

segment of the 64-bit internal resource is accessed during The Device Select register is used to select a specific (target)

a particular data cycle on the 16-bit data bus. The actual device. The TCO DS instruction sets the 16-bit DS register

destination for data writes and source for data reads (called to the value of the following Command Write cycle. The DS

the persistent destination and source) are set independently register can be read. A device is selected when its DS is

with SPD and SPS instructions, respectively.

equal to its PA value. In a daisy chain, setting DS = FFFFH

will select all devices. However, in this case, the ability to

Each of the two counters consists of a start limit, an end read information out of the device is restricted as shown in

limit, and the current count value which points to the Tables 5a and 5b. A software reset (using the Control

segment to be accessed on the next data cycle. The register) does not affect the Device Select register.

current count value can be set to any segment, even if it

is outside the range set by the start and end limits. The Address Register (AR)

counters count up from the current count value to the The Address register points to the CAM memory location

end limit and then jump back to the start limit. If the to be operated upon when M@[AR] or M@aaaH is part

current count is greater than the end limit, the current of the instruction. It can be loaded directly by using a

count value will increment to 3, then roll over to 0 and TCO AR instruction or indirectly by using an instruction

continue incrementing until the end limit is reached; it requiring an absolute address, such as MOV aaaH,CR,V.

F

then jumps back to the start limit.

After being loaded, the Address register value will then

9

Rev. 3a

Share Link: