MU9C4480A-12DC Просмотр технического описания (PDF) - Music Semiconductors

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MU9C4480A-12DC

LANCAMs®

Music Semiconductors 

MU9C4480A/L

OPERATIONAL CHARACTERISTICS Continued

edge of /E, and the Data outputs are enabled while /E is LOW.

When reading from the persistently selected data source, the

Source Segment counter is clocked by the rising edge of /E.

THE REGISTER SET

The Control, Segment Control, Address, Mask Register 1,

and the Persistent Source and Destination registers are

duplicated, with one set termed the Foreground set, and

the other the Background set. The active set is chosen by

issuing Select Foreground Registers or Select Background

Registers instructions. By default, the Foreground set is

active after a reset. Having two alternate sets of registers

that determine the device configuration allows for a rapid

return to a foreground network filtering task from a

background housekeeping task.

Writing a value to the Control register or writing data to the

last segment of the Comparand or either mask register will

cause an automatic comparison to occur between the

contents of the Comparand register and the words in the

CAM segments of the memory marked valid, masked by

MR1 or MR2 if selected in the Control register.

Instruction Decoder

The Instruction decoder is the write-only decode logic for

instructions and is the default destination for Command

Write cycles. If an instruction’s Address Field flag (bit 11)

is set to a 1, it is a two-cycle instruction that is not executed

immediately. For the next cycle only, the data from a

Command Write cycle is loaded into the Address register

and the instruction then completes at that address. The

Address register will then increment, decrement, or stay at

the same value depending on the setting of Control Register

bits CT3 and CT2. If the Address Field flag is not set, the

memory access occurs at the address currently contained

in the Address register.

Control Register (CT)

The Control register is composed of a number of switches

that configure the LANCAM, as shown in Table 8 on page

20. It is written or read using a TCO CT instruction. If bit 15

of the value written during a TCO CT is a 0, the device is

reset (and all other bits are ignored). See Table 4 for the

Reset states. Bit 15 always reads back as a 0. A write to the

Control register causes an automatic compare to occur

(except in the case of a reset). Either the Foreground or

Background Control register will be active, depending on

which register set has been selected, and only the active

Control register will be written to or read from.

If the Match Flag is disabled through bits 14 and 13, the

internal match condition, /MA(int), used to determine a

daisy-chained device’s response is forced HIGH as shown

in Tables 5a and 5b on page 11, so that Case 6 is not

possible, effectively removing the device from the daisy

chain. With the Match Flag disabled, /MF=/MI and

operations directed to Highest-priority Match locations

are ignored. Normal operation of the device is with the /MF

enabled. The Match Flag Enable field has no effect on the

/MA or /MM output pins or Status Register bits. These

bits always reflect the true state of the device.

If the Full Flag is disabled through bits 12 and 11, the

device behaves as if it is full and ignores instructions to

Next Free address. Additionally, writes to the Page

Address register will be disabled. All other instructions

operate normally. Additionally, with the /FF disabled, /FF=/FI.

Normal operation of the device is with the /FF enabled.

The Full Flag Enable field has no effect on the /FL Status

Register bit. This bit always reflects the true state of the

device.

The IEEE Translation control at bit 10 and bit 9 can be used

to enable the translation hardware for writes to 64-bit

resources in the device. When translation is enabled, the

bits are reordered as shown in Figure 2.

Control Register bits 8–6 control the CAM/RAM

partitioning. The CAM portion of each word may be sized

from a full 64 bits down to 16 bits in 16-bit increments. The

RAM portion can be at either end of the 64-bit word.

Compare masks may be selected by bits 5 and 4. Mask

Register 1, Mask Register 2, or neither may be selected to

mask compare operations. The address register behavior

is controlled by bits 3 and 2, and may be set to increment,

decrement, or neither after a memory access. Bits 1 and 0

set the operating mode: Standard as shown in Table 5a, or

Enhanced as shown in Table 5b. The device will reset to

the Standard mode, and follow the operating responses in

D Q15

DQ8 DQ7

D Q0

D Q15

DQ8 DQ7

D Q0

Figure 2: IEEE 802.3/802.5 Format Mapping

7

Rev. 3a

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