MU9C4480A-12DC Просмотр технического описания (PDF) - Music Semiconductors
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MU9C4480A-12DC Datasheet PDF : 28 Pages
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OPERATIONAL CHARACTERISTICS Continued
MU9C4480A/L
Case
1
2
3
4
5
62
Internal Internal External
/EC(int) /MA (int)
/MI
Device Select Command Data Write Command Data Read
Reg.
Write1
Read
1
X
X
DS=FFFFH
YES3
YES4
NO
NO
1
X
X
DS=PA
YES3
YES4
YES
YES
1
X
X
DS≠FFFFH and
NO
NO
NO
NO
DS≠PA
0
X
0
X
NO
NO
NO5
NO
0
1
1
X
NO
NO
NO5
NO
0
0
1
X
YES3
YES4
YES5
YES
Table 5a: Standard Mode Device Select Response
Case
Internal Internal External
/EC(int) /MA (int)
/MI
Device Select Command Data Write Command Data Read
Reg.
Write1
Read
1
1
X
X
DS = FFFFH
YES3
YES4
NO
NO
2
1
X
X
DS = PA
YES3
YES4
YES
YES
3
1
X
X
DS ≠ FFFFH
NO
NO
NO
NO
and DS ≠ PA
4
0
0
0
5
0
1
X
62
0
0
1
X
YES3,6
YES4,7
NO5
NO
X
YES3,6
YES4,7
NO5
NO
X
YES3
YES4
YES5
YES
NOTES:
Table 5b: Enhanced Mode Device Select Response
1. Exceptions are:
A) A write to the Device Select register is always active in all devices;
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.
2. If /MF is disabled in the Control register, /MA (Internal) is forced HIGH preventing a Case 6 response.
3. This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.
4. This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.
5. For a Command Read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain
(i.e., /FI LOW and /FF HIGH) and NO if it does not.
6. This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.
7. This is NO if the Persistent Destination is Memory at Highest-Priority match.
THE MEMORY ARRAY
Memory Organization
The Memory array is organized into 64-bit words with each
word having an additional two validity bits (Skip and Empty).
By default, all words are configured to be 64 CAM cells.
However, bits 8–6 of the Control register can divide each word
into a CAM field and a RAM field. The RAM field can be
assigned to the least-significant or most-significant portion
of each entry. The CAM/RAM partitioning is allowed on 16-
bit boundaries, permitting selection of the configuration
shown in Table 8 on page 20, bits 8–6 (e.g., 001 sets the 48
MSBs to CAM and the 16 LSBs to RAM). Memory Array bits
designated as RAM can be used to store and retrieve data
associated with the CAM content at the same memory location.
Memory Access
There are two general ways to get data into and out of the
memory array: directly or by moving the data through the
Comparand or mask registers.
The first way, through direct reads or writes, is set up by
issuing a Set Persistent Destination (SPD) or Set Persistent
Source (SPS) command. The addresses for the direct access
can be directly supplied; supplied from the Address register,
supplied from the Next Free Address register, or supplied as
the Highest-Priority Match address. Additionally, all the direct
writes can be masked by either mask register.
The second way is to move data via the Comparand or mask
registers. This is accomplished by issuing Data Move
commands (MOV). Moves using the Comparand register can
also be masked by either of the mask registers.
11
Rev. 3a
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