5962R3829435SNA Просмотр технического описания (PDF) - Aeroflex UTMC
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5962R3829435SNA Datasheet PDF : 15 Pages
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NC
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
DQ0
11
DQ1
12
DQ2
13
Vss
14
28
VDD
27
W
26
E2
25
A8
24
A9
23
A11
22
G
21
A10
20
E1
19
DQ7
18
DQ6
17
DQ5
16
DQ4
15
DQ3
Figure 2. SRAM Pinout
PIN NAMES
A(12:0) Address
DQ(7:0) Data Input/Output
E1 Enable 1
E21 Enable 2
W Write
G Output Enable
VDD Power
VSS Ground
DEVICE OPERATION
The UT67164 has four control inputs called Enable 1 (E1),
Enable 2 (E2), Write Enable (W), and Output Enable (G); 13
address inputs, A(12:0); and eight bidirectional data lines,
DQ(7:0). E1 and E2 are device enable inputs that control device
selection, active, and standby modes. Asserting both E1 and E2
enables the device, causes IDD to rise to its active value, and
decodes the 13 address inputs to select one of 8,192 words in
the memory. W controls read and write operations. During a
read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
W
E1
E2 I/O Mode Mode
X1
X
X
0 3-state
Standby
X
X
1
X 3-state
Standby
X
0
0
1 Data in Write
1
1
0
1 3-state
Read2
0
1
0
1 Data out Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min), E1 less than VIL
(max), and E2 greater than V IH (min) defines a read cycle. Read
access time is measured from the latter of device enable, Output
Enable, or valid address to valid data output.
Read Cycle 1, the Address Access read in figure 3a, is initiated
by a change in address inputs while the chip is enabled with G
asserted and W deasserted. Valid data appears on data outputs
DQ(7:0) after the specified tAVQV is satisfied. Outputs remain
active throughout the entire cycle. As long as device enable and
output enable are active, the address inputs may change at a rate
equal to the minimum read cycle time (tAVAV ).
Figure 3b shows Read Cycle 2, the Chip Enable-controlled
Access. For this cycle, G remains asserted, W remains
deasserted, and the addresses remain stable for the entire cycle.
After the specified tETQV is satisfied, the eight-bit word
addressed by A(12:0) is accessed and appears at the data outputs
DQ(7:0).
Figure 3c shows Read Cycle 3, the Output Enable-controlled
Access. For this cycle, E1 and E2 are asserted, W is deasserted,
and the addresses are stable before G is enabled. Read access
time is tGLQV unless tAVQV or tETQV have not been satisfied.
2
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