HS-1412RH Просмотр технического описания (PDF) - Intersil
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HS-1412RH Datasheet PDF : 11 Pages
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HS-1412RH
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board (PCB). The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
50
Evaluation Board
The performance of the HS-1412RH may be evaluated using
the HA5025 Evaluation Board, slightly modified as follows:
1. Remove the four feedback resistors, and leave the
connections open.
2. a. For AV = +1 evaluation, remove the gain setting
resistors (R1), and leave pins 2, 6, 9, and 13 floating.
b. For AV = +2, replace the gain setting resistors (R1) with
0Ω resistors to GND.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
To order evaluation boards (part number HA5025EVAL),
please contact your local sales office.
OUT
50Ω
1
R 1(NOTE)
2
IN
3
50Ω
4
+5V
10µF
5
0.1µF 6
7
14
NOTE: R1 = ∞ (AV = +1)
13
-
+
or 0Ω (AV = +2)
12
11
-5V
10
0.1µF 10µF
9
8
GND
GND
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
40
30
20
AV = +1
AV = +2
10
FIGURE 3A. TOP LAYOUT
0
0
50 100 150 200 250 300 350 400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
RS and CL form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
350MHz. By decreasing RS as CL increases (as illustrated in
the curves), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth decreases as
the load capacitance increases. For example, at AV = +2,
RS = 22Ω, CL = 100pF, the overall bandwidth is 125MHz, and
bandwidth drops to 100MHz at RS = 12Ω, CL = 220pF.
3
FIGURE 3B. BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
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