CD4031BMS Просмотр технического описания (PDF) - Intersil
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CD4031BMS Datasheet PDF : 10 Pages
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CD4031BMS
Logic Diagram
*
15
DATA 1 IN
*
10
MODE CONTROL
*
1
RECIRCULATE
(DATA 2 IN)
CL
p
n
CL
CL
CL
p
n
CL
CL
CL
p
p
n
n
63 IDENTICAL
STAGES
CL
CL
CL
*
2
CLOCK
p
n
CL
CL
CL
p
9 CLD
n
CL
CL
CL
p
n
CL
CL
p
n
CL
p
VDD
n
CL
*ALL INPUTS ARE
CL
PROTECTED BY
p
CMOS/MOS PROTECTION
NETWORK
n
VSS
CL
7
6
Q
Q
5
Q’
INPUT CONTROL CIRCUIT
TRUTH TABLE
BIT INTO
DATA RECIR MODE STAGE 1
1
X
0
1
0
X
0
0
X
1
1
1
X
0
1
0
1 = High Level
X = Don’t Care
0 = Low Level
NC = No Change
TYPICAL STAGE TRUTH TABLE
DATA
CL
DATA + 1
0
0
1
1
X
NC
1 = High Level
X = Don’t Care
0 = Low Level
NC = No Change
TRUTH TABLE FOR OUTPUT FROM Q’
(TERMINAL 5)
DATA + 64
DATA + 64
CL
1/2
0
0
1
1
X
NC
1 = High Level
X = Don’t Care
0 = Low Level
NC = No Change
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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