UT1750AR12WCC Просмотр технического описания (PDF) - Aeroflex UTMC
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UT1750AR12WCC Datasheet PDF : 56 Pages
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OPERAND BUSSES
PIN NAME
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PIN NUMBER
FLTPK PGA
84
A14
85
B12
86
C11
87
A13
88
B11
89
A12
90
C10
91
B10
92
B9
93
C9
94
A10
95
A9
96
B8
97
A8
102
A7
103
A6
64
H15
69
G15
70
F15
71
G14
72
F14
73
F13
74
E15
75
D15
76
C15
77
D14
78
E13
79
C14
80
B15
81
D13
82
C13
83
B14
TYPE
TTO
TTB
ACTIVE
AH
AH
DESCRIPTION
Address Bus - Operand. When asserted, this bus is
unidirectional and represents the Operand Address. The bus
is in the high-impedance state when the UT1750AR does
not control the bus. A15 is the most significant bit. The
Operand Address enters a high-impedance state when the
UT1750AR is in the test mode (TEST = 0).
Data Bus - Operand. This bidirectional data bus remains
in a high-impedance state when the UT1750AR does not
control the bus. D15 is the most significant bit. The
Operand Data Bus enters a high-impedance state when
the UT1750AR is in the test mode (TEST = 0).
RISC BUSSES
PIN NAME
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RA10
RA11
RA12
RA13
RA14
RA15
PIN NUMBER
FLTPK PGA
18
R2
19
P4
20
N5
21
R3
22
P5
23
R4
24
N6
25
P6
26
P7
27
N7
28
R6
29
R7
30
P8
31
R8
36
R9
37
R10
TYPE
TTO
ACTIVE
AH
DESCRIPTION
RISC (Instruction) Address Bus. This unidirectional bus
represents the address of the data in RISC memory. With the
MIL-STD-1750A mode of operation selected (M1750 = 1),
the data from RISC memory is from the emulation ROMs. This
data is the RISC instructions that the UT1750AR executes to
emulate MIL-STD-1750A instructions. RA15 is the most
significant bit. The RISC address enters a high-impedance
state when the UT1750AR is in the test mode (TEST = 0).
Continued on page 10.
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