UT1750AR12WCC Просмотр технического описания (PDF) - Aeroflex UTMC
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UT1750AR12WCC Datasheet PDF : 56 Pages
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Standard Products
UT1750AR RISC Microprocessor
Data Sheet
Oct. 1998
FEATURES
q Operates in either RISC (Reduced Instruction Set
Computer) mode or MIL-STD-1750A mode
q Registers may be in 16-bit word or 32-bit double-word
configurations
q Supports MIL-STD-1750A 32-bit floating-point
q Built-in multiprocessor bus arbitration and Direct Memory
operations and 48-bit extended-precision
Access support (DMA)
floating-point operations on chip
q Built-in 9600 baud UART
q Supports defined MIL-STD-1750A Console Mode of
Operation
q TTL-compatible I/O
q Stable 1.5-micron CMOS technology
q Standard Military Drawing available
q Full 64K-word address space. Expandable to 1M words with
optional MMU (operand port)
q Register-oriented architecture has 21 user-accessible
q Full military operating range, -55°C to +125°C,
screened to specific test methods listed in Table I MIL-
STD-883 Method 5004, Class B
registers
OE
WE
BRQ
BGNT
BUSY
BGACK
NUI1
NUI2
M1750
RISC
MEMORY
CONTROL
BUS
ARBITRA-
TION
PROCES-
SOR
STATUS
OSCOUT
16
OSCIN SYSCLK
OSCILLATOR
/CLOCK
GENERAL
PURPOSE
REGISTERS
SHIFT REG 32
32 BIT REG 32
UART
TBR
RBR
TR 16
TB 16
TIMCLK
TEST
UARTOUT
UARTIN
STATE1
MME
NUO3
CONSOLE
PROCESSOR
CONTROL
LOGIC
TEMP DEST TEMP SRC
IM 16
FR 16
PI 16
ST 16
I/O
MUX
IR
RISC MAP
SW 16
32
RISC DATA
16
32
32
4 PS0-3
RISC
ADDRESS 4
or O/P DISC
RISC 16
ADDRESS
SYSFLT
BTERR
MPAR
MPROT
PFAIL
IOLINT1
IOLINT0
INT0-5 6
RISC
ADD
MUX
I
N
T
E
R
R
U
P
T
S
IC/ICs
32
ACC
32
A MUX
B MUX
32-BIT ALU
8
16
PIPELINE
BUS
PR
CONTROL
1750 SP 16
32
1750 PC 16
16
ADDR
MUX
AS0-3
OPERAND
DATA
OP/IN
DTACK
M/IO
R/WR
AS
DS
OPERAND
ADDRESS
MRST
Figure 1. UT1750AR Functional Block Diagram
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