XE1212C Просмотр технического описания (PDF) - Xecom

Номер в каталоге

Компоненты Описание

производитель

XE1212C

1200bps Modem Module with Parallel Host Interface

Xecom 

Interrupt Enable Register

This 8-bit register enables the four interrupt sources of the XE1212C to separately activate the Interrupt line (INT,

pin 13). It is possible to totally disable the Interrupt system by resetting bits 0 through 3 of the Interrupt Enable

Register. similarly, by setting the appropriate bits of this register to a logic 1, selected interrupts can be enabled.

Disabling the interrupt system inhibits the Interrupt Identification Register and the active (high) INT output from the

XE1212C. All other system functions operate in their normal manner, including the setting of the Line Status and

Modem Status Register. The contents of the Interrupt Enable Register are described below.

IER Bit

Bit 0:

Bit 1:

Bit 2:

Bit 3:

Bit 4-7:

Description

This bit enables the Received Data Available Interrupt when set to logic 1.

This bit enables the Transmitter Holding Register Empty Interrupt when set to a logic 1.

This bit enables the Receiver Line Status Interrupt when set to logic 1.

This bit enables the MODEM Status Interrupt when set to logic 1.

These four bits are always logic 1.

Line Control Register

Bit 0-1:

Bit 2:

Bit 3:

Bit 4:

Bit 5:

Bit 6:

Bit 7:

Bits 0 and 1 specify the number of bits in each transmitted or received character. the encoding of

the bits is as follows:

Bit 1 Bit 0 WORD LENGTH

0

0

5 Bits

0

1

6 Bits

1

0

7 Bits

1

1

8 Bits

This bit specifies the number of stop bits in each transmitted or received character. If bit 2 is a

logic 0, one stop bit is generated or checked in the transmit or receive data, respectively. If bit 2 is

a logic 1 when 7-bit word length with no Parity is selected, two stop bits are generated or checked.

This bit is the Parity Enable bit. When bit 0 is a logic 0 and bit 3 is a logic 1, a Parity bit is

generated (transmit data) or checked (receive data) between the last data word bit and the Stop

bit of the serial data. (The Parity bit is used to verify that the data has been transmitted intact.)

This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic 0, an odd parity

is transmitted or checked for in the received data. When bit 3 is a logic 1 and bit 4 is a logic 1,

even parity is transmitted or checked.

This bit is the Stick Parity bit. when bit 3 is a logic 1 and bit 5 is a logic 1, a 1 is placed in the

parity bit.

This bit is the Set Break Control bit. When bit 6 is a logic 1, the modem output is forced to the

Space state (logic 0) and remains there until reset regardless of other transmitter activity. This

feature enables the CPU to alert a terminal in a computer communications system.

This bit is the Divisor Latch Access bit (DLAB). It must be set high (logic 1) to access the Divisor

Latches of the Baud Rate Generator during a Read or Write operation. It must be set low (logic 0)

to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.

XECOM

(7)

XE1212C

Share Link: