XE1212C Просмотр технического описания (PDF) - Xecom
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XE1212C Datasheet PDF : 16 Pages
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UART Register Addresses
DLAB A2 A1 A0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
1
0
X
0
1
1
X
1
0
0
X
1
0
1
X
1
1
0
X
1
1
1
1
0
0
0
1
0
0
1
REGISTER
Receiver Buffer (read only) (RBR)
Transmitter Holding (write only) (THR)
Interrupt Enable (IER)
Interrupt Identification (read only) (IIR)
Line Control (LCR)
Modem Control (MCR)
Line Status (LSR)
Modem Status (read only) (MSR)
Scratch Register (Not Used by the Modem)
Divisor Latch (DLL)
Divisor Latch (DLM)
Interrupt Identification Register
The XE1212C Interrupt capability emulates the industry standard 8250 UART. This minimizes software overhead
during data character transfers, the XE1212C prioritizes interrupts into four levels. The Interrupt Identification
Register indicates that an interrupt is pending and identifies the source of the interrupt. When this register is
addressed during chip select time, it freezes the highest priority interrupt pending and no other interrupts are
acknowledged until the CPU services that interrupt. The table below defines the interrupt priorities and the contents
of the Interupt Identification Register.
IIR Register Bit
Description
0
Bit 1
1
0
1
0
Bit 2
1
1
0
o
This bit indicates if an interrupt is pending. When bit 0 is a logic 0, an interrupt is pending
and the IIR contents may be used as a pointer to the appropriate interrupt service
routine. When bit 0 is logic 1, no interrupt is pending.
Interupt Priority
(priority 1)
(priority 2)
(priority 3)
(priority 4)
Interrupt Definition
Receiver Line Status
Received Data Ready
Transmitter Holding Register Empty
MODEM Status
3-7
These five bits of the Interrupt Identification Register are always a logic 0.
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(6)
XE1212C
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