STLC5444
Figure 1a: Microprocessor Read Timing non multiplexed mode.
ALE
tAHRH
AO
CS
RD
DATA
tCLRL (Note 1)
tASRL
tADDA
tRLRH
tRLDA
tRHCH (Note 2)
tRHDZ
Read Data
tRHRL
D97TL301A
Notes:
1 - If tCLRL is negative, tRHRL, tRLRH, tAZRL, and tRLDA are measured from CS rather than RD.
2 - If tRHCH is negative, tRHRL, tRLRH and tRHDZ are measured from CS rather than RD.
When a read from the LER immediately follows a write to the LER a minimum of 1 µs is required between these operations.
Figure 2a: Microprocessor Write Timing non multiplexed mode.
ALE
tASWL
tAHWH
AO
tWHCH (Note 2)
CS
WR
DATA
INT
tCLWL (Note 1)
tWLWH
tDAWH
tWHDZ
Write Data
(Note 3)
tWHWL
D97TL302A
Notes:
1 - If tCLWL is negative tWHWL and tWLWH are measured from CS rather than WR.
2 - If tWHCH is negative, tWHWL, tWLWH, tDAWH and tWHDZ are measured from CS rather than WR.
The propagation delay from the writing of the T/I bit to the effect on the INT pin is approximately 1µs for both mask and enable operations.
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