PM5316-BI Просмотр технического описания (PDF) - PMC-Sierra
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PM5316-BI Datasheet PDF : 491 Pages
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SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)
Production
10.2 Receive Section Overhead Processor (RSOP) ................................................49
10.3 Receive Section Trace Buffer (SSTB)...............................................................51
10.4 Receive Line Overhead Processor (RLOP) ......................................................52
10.5 The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE) ...54
10.6 Receive Transport Overhead Controller (RTOC)..............................................55
10.7 Ring Control Port...............................................................................................55
10.8 Receive De-multiplexer (RX_DEMUX) .............................................................56
10.9 Receive Path Processing Slice (RPPS)............................................................56
10.10 Transmit Path Processing Slice (TPPS) ...........................................................70
10.11 Transmit Multiplexer (TX_REMUX)...................................................................76
10.12 Transmit Transport Overhead Controller (TTOC) .............................................76
10.13 Transmit Line Overhead Processor (TLOP) .....................................................78
10.14 Transmit Section Overhead Processor (TSOP)................................................79
10.15 Transmit Section Trace Buffer (SSTB)..............................................................80
10.16 Transmit Line Interface .....................................................................................80
10.17 Add/Drop Bus Time-Slot Interchange (TSI) ......................................................80
10.18 System Side Interfaces .....................................................................................82
10.19 JTAG Test Access Port Interface ......................................................................83
10.20 Microprocessor Interface ..................................................................................83
11 Normal Mode Register Descriptions ...........................................................................94
12 Test Features Description .........................................................................................382
12.1 Master Test and Test Configuration Registers ................................................382
12.2 JTAG Test Port ................................................................................................386
13 Operation ..................................................................................................................393
13.1 Software Initialization Sequence.....................................................................393
13.2 SONET/SDH Overhead Byte Processing .......................................................393
13.3 Path Processing Slice Configuration Options .................................................399
13.4 Time Slot Interchange (Grooming) Configuration Options..............................401
13.5 System Interface Configuration Options .........................................................403
13.6 Bit Error Rate Monitor (BERM) .......................................................................403
13.7 Clocking Options .............................................................................................404
13.8 Loopback Modes.............................................................................................406
13.9 Loopback Operation........................................................................................409
13.10 JTAG Support..................................................................................................410
13.11 Board Design Recommendations ...................................................................415
Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use
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Document ID: PMC-1990822, Issue 4
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