WM2604IDT Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM2604IDT

Quad 10-Bit Serial Input Voltage Output DAC

Wolfson Microelectronics plc 

WM2604

SERIAL INTERFACE

SCLK

DIN

1

tSUD

tHD

D15

tSUCSFS

tWL

tWH

2

3

D14

D13

NCS

tWHFS

FS

tSUFSCLK

4

5 15

16

D12

D1

D0

Production Data

tSUC16CS

tSUC16FS

Figure 1 Timing Diagram

Test Conditions:

RL = 10kΩ, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over

recommended operating free-air temperature range (unless noted otherwise)

SYMBOL TEST CONDITIONS

MIN

tSUCSFS

Setup time NCS low before negative FS edge.

10

tSUFSCLK

Setup time FS low before first negative SCLK edge.

8

Setup time, sixteenth negative SCLK edge after FS low

tSUC16FS

on which D0 is sampled before rising edge of FS.

10

Setup time, sixteenth positive SCLK edge (first positive

10

after D0 sampled) before NCS rising edge.

tSUC16CS

If FS is used instead of the sixteenth positive edge to

update the DAC, then the setup time is between the FS

rising edge and the NCS rising edge.

tWHCLK

Pulse duration, SCLK high.

25

tWLCLK

Pulse duration, SCLK low.

25

tSUDCLK

Setup time, data ready before SCLK falling edge.

8

tHDCLK

Hold time, data held valid after SCLK falling edge.

5

tWHFS

Pulse duration, FS high.

20

TYP

MAX

UNIT

ns

ns

ns

ns

ns

ns

ns

ns

ns

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 June 1999

6

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