TM-1000 Просмотр технического описания (PDF) - Philips Electronics

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TM-1000

Programmable Media Processor

Philips Electronics 

DEDICATED INSTRUCTION AND DATA CACHE

TM-1000’s CPU is supported by separate, dedicated on-chip data and

instruction caches. To improve cache behavior and performance, both

caches have a locking mechanism. Cache coherency is maintained by

software.

Data cache is dual-ported to allow two simultaneous accesses. It is

non-blocking, thus handling cache misses and CPU cache accesses can

proceed simultaneously. Early restart techniques reduce read-miss

latency. Background copyback reduces CPU stalls. Partial word (8-bit

and 16-bit) memory operations are supported.

To reduce internal bus bandwidth requirements, instructions in main

memory and cache use a compressed format. Instructions are decom-

pressed in the instruction cache decompression unit before being

processed by the CPU.

No external second-level cache is required to deliver media perfor-

mance an order of magnitude more than x86 processors.

GLUELESS MEMORY SYSTEM INTERFACE

The TM-1000 memory system balances cost and performance by cou-

pling substantial on-chip caches with a glueless interface to synchronous

DRAM (SDRAM). Higher bandwidth SDRAM permits the TM-1000

to use a narrower and simpler interface than would be required to

achieve similar performance with standard DRAM.

TM-1000’s memory interface provides sufficient drive capacity for an

up to 100-MHz, 8-MB memory system (four 2Mx8 SDRAMS).

Larger memories can be implemented by using lower memory system

clock frequencies or external buffers. Programmable speed ratios allow

SDRAM to have a different clock speed than the TM-1000 CPU.

Support for a variety of memory types, speeds, bus widths, and off-

chip bank sizes allow a range of TM-1000-based systems to be

configured.

HIGH-SPEED INTERNAL BUS (DATA HIGHWAY)

TM-1000’s internal bus, or data highway, connects all internal func-

tion units together and provides access to control registers in each

function unit, to external SDRAM, and to the external PCI bus. It

consists of separate 32-bit data and address buses; bus transactions use

a block transfer protocol. On-chip peripheral units and coprocessors

can be masters or slaves on the bus. Programmable bandwidth alloca-

tion enables the data highway to maintain real-time responsiveness in

a variety of applications.

Unique to the TriMedia

processor’s VLIW

implementation,

parallelism is

optimized at compile

time by the TriMedia

compilation system.

SDRAM

VIDEO IN

MAIN MEMORY

INTERFACE

VLD COPROCESSOR

AUDIO IN

VIDEO OUT

AUDIO OUT

I2C INTERFACE

VLIW CPU

INSTR.

CACHE

DATA

CACHE

TIMERS

SYNCHRONOUS

SERIAL INTERFACE

IMAGE

COPROCESSOR

PCI INTERFACE

TO

PCI BUS

TM-1000 ARCHITECTURE

On a single chip, the TM-1000 incorporates a powerful VLIW CPU

and peripherals to accelerate processing of audio, video, graphics,

and communications data.

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