STLVD111(2002) Просмотр технического описания (PDF) - STMicroelectronics
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STLVD111 Datasheet PDF : 12 Pages
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STLVD111
DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise
specified (Note 1, 2)
Symbol
Parameter
Test Conditions
Value
Unit
Min. Typ. Max.
VBB
ICCD
CIN
COUT
VIH
VIL
II
Output Reference Voltage
Power Supply Current
Input Capacitance
Output Capacitance
Logic Input High Threshold
Logic Input Low Threshold
Logic Input Current
VCC = 2.5 V
All driver enabled and loaded
1.15 1.25 1.35
V
125 160 mA
VI = 0V to VCC
5
pF
5
pF
VCC = 2.5 V
2
VCC = 2.5 V
VCC = 2.5 V, VIN = VCC or GND
V
0.8
V
±10
µA
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground
unless otherwise specified.
NOTE 2: All typical values are given for VCC = 2.5V and TA = 25°C unless otherwise stated.
LVDS TIMING CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified
(Note 4)
Symbol
Parameter
Test Conditions
Value
Unit
Min. Typ. Max.
tTLH, tTHL Transition Time
RL = 100 Ω, CL = 5 pF, Fig. 5, 6)
220 300
ps
tPHL, tPLH Propagation Delay Time
(Fig. 5, 6)
2
2.5
ns
fMAX Maximum Input Frequency
700 900
MHz
tSKEW Bank Skew
Part to Part Skew
(Fig. 1)
(Fig. 2)
50
ps
100
Pulse Skew
(Fig. 3)
50
NOTE 4: Generator waveforms for all test conditions: f=1MHz, ZO = 50 Ω (unless otherwise specified).
CONTROL REGISTER TIMING CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, EN=H, unless
otherwise specified (Figure 4)
Symbol
Parameter
Test Conditions
Value
Unit
Min. Typ. Max.
fMAX
ts
th
trem
tW
Maximum Frequency of Shift
Register
Clock to SI Setup Time
Clock to SI Hold Time
Enable to Clock Removal Time
Minimum Clock Pulse Width
(Fig. 7)
(Fig. 7)
(Fig. 7)
(Fig. 7)
(Fig. 7)
100 150
3
MHz
2
ns
1.5
ns
1.5
ns
ns
4/12
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