UPD7225GB-3B7 Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD7225GB-3B7

PROGRAMMABLE LCD CONTROLLER/DRIVER

NEC => Renesas Technology 

µPD7225

2. INTERNAL SYSTEM CONFIGURATION

2.1 Serial Interface

The serial interface consists of an 8-bit serial register and a 3-bit SCK counter.

The serial register clocks in the serial data from the SI pin at the rising edge of /SCK. At the same time, the SCK

counter increments (+1) the serial clock. As a result, if an overflow occurs (when eight pulses are counted), input

from the SI pin is disabled (/BUSY = 0), and the contents of the serial register is output to the command/data register.

The /SCK should be set to high before serial data is input and after the data has been input (after eight clocks are

input to /SCK).

Serial data must be input to the SI pin beginning with MSB first.

SI pin

MSB

LSB

D7 D6 D5 D4 D3 D2 D1 D0

µ PD7225

2.2 Command/Data Register

The command/data register latches the contents of the serial register in order to process the serial data clocked

into the serial register. After the serial data is latched, if the clocked in data is specified as command, the

command/data register transfers its contents to the command decoder. If specified as data the command/data

register transfers its contents to data memory or the segment decoder.

2.3 Command Decoder

When the contents of the command/data register are specified as a command (C, /D was high when data was

input), the command decoder, clocks in the contents of the command/data register and controls the µPD7225.

2.4 Segment Decoders

The µPD7225 has a 7-segment decoder for use with divide-by-3 and divide-by-4 time division, and a 14-segment

decoder for use divide-by-4 time division.

The 7-segment decoder can generate signals for numeric characters 0 to 9 and six different symbols. The 14-

segment decoder can generate signals for 36 alphanumeric characters and 13 different symbols. When the WITH

SEGMENT DECODER command is executed, if the contents of the command/data register are specified as data, the

contents will be input to the segment decoder, and converted to display codes, and then automatically written to the

data memory. Whether to select the 7-segment decoder or 14-segment decoder is determined by the most

significant bit (bit 7) of the data input to the segment decoder. It the most significant bit is 0, the 7-segment decoder

will be selected. If it is 1, the 14-segment decoder will be selected. If the 7-segment decoder is selected (however,

divide-by-3 and divide-by-4 time division), the lower 4 bits (bit 3 to bit 0) of the input data (C, /D = 0) will be decoded

and written to the data memory.

If the 14- segment decoder is selected (however, divide-by-4 time division), the lower 7 bits of the input data (C, /D

= 0) will be decoded and written to the data memory.

8

Data Sheet S14308EJ6V0DS00

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