µPD7225
Static
Figure 1-2. /SYNC Pin Status after Reset (/RESET = 1)
1 frame
COM0
/SYNC
Divie-by-2
time division
COM0
/SYNC
Divie-by-3
time division
COM0
/SYNC
Divie-by-4
time division
COM0
/SYNC
1 frame
1 frame
1 frame
1.7 /RESET……Input
This is an active low reset input pin.
1.8 S0-S31 (Segment)……Output
These pins output segment drive signals.
1.9 COM0-COM3 (COMmon)……Output
These pins output common drive signals.
1.10 CL1, CL2 (Clock)
A resistor is connected across these pins for internal clock generation. When inputting an external clock, use the
CL1 pin for input.
1.11 VLC1, VLC2, VLC3
LCD driver power supply pin.
6
Data Sheet S14308EJ6V0DS00