8254 Просмотр технического описания (PDF) - Intel
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8254 Datasheet PDF : 21 Pages
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8254
Control Word Counter 0
LSB of count Counter 0
MSB of count Counter 0
Control Word Counter 1
LSB of count Counter 1
MSB of count Counter 1
Control Word Counter 2
LSB of count Counter 2
MSB of count Counter 2
A1 A0
1
1
0
0
0
0
1
1
0
1
0
1
1
1
1
0
1
0
Control Word Counter 2
Control Word Counter 1
Control Word Counter 0
LSB of count Counter 2
MSB of count Counter 2
LSB of count Counter 1
MSB of count Counter 1
LSB of count Counter 0
MSB of count Counter 0
A1 A0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
Control Word Counter 0
Control Word Counter 1
Control Word Counter 2
LSB of count Counter 2
LSB of count Counter 1
LSB of count Counter 0
MSB of count Counter 0
MSB of count Counter 1
MSB of count Counter 2
A1 A0
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
1
1
0
Control Word Counter 1
Control Word Counter 0
LSB of count Counter 1
Control Word Counter 2
LSB of count Counter 0
MSB of count Counter 1
LSB of count Counter 2
MSB of count Counter 0
MSB of count Counter 2
A1 A0
1
1
1
1
0
1
1
1
0
0
0
1
1
0
0
0
1
0
NOTE
In all four examples all Counters are programmed to read write two-byte counts These are only four of many possible
programming sequences
Figure 8 A Few Possible Programming Sequences
Read Operations
It is often desirable to read the value of a Counter
without disturbing the count in progress This is easi-
ly done in the 8254
There are three possible methods for reading the
counters a simple read operation the Counter
Latch Command and the Read-Back Command
Each is explained below The first method is to per-
form a simple read operation To read the Counter
which is selected with the A1 A0 inputs the CLK
input of the selected Counter must be inhibited by
using either the GATE input or external logic Other-
wise the count may be in the process of changing
when it is read giving an undefined result
COUNTER LATCH COMMAND
The second method uses the ‘‘Counter Latch Com-
mand’’ Like a Control Word this command is written
to the Control Word Register which is selected
when A1 A0 e 11 Also like a Control Word the
SC0 SC1 bits select one of the three Counters but
two other bits D5 and D4 distinguish this command
from a Control Word
A1 A0 e 11 CS e 0 RD e 1 WR e 0
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 0 0 X X X X
SC1 SC0 specify counter to be latched
SC1 SC0
Counter
00
0
01
1
10
2
1 1 Read-Back Command
D5 D4 00 designates Counter Latch Command
X don’t care
NOTE
Don’t care bits (X) should be 0 to insure compatibility
with future Intel products
Figure 9 Counter Latching Command Format
7
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