SY89430V(2000) Просмотр технического описания (PDF) - Micrel
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SY89430V Datasheet PDF : 9 Pages
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Micrel
ClockWorks™
SY89430V
WITH 16MHZ INPUT
VCO Frequency
(MHz)
400
402
404
406
•
•
•
944
946
948
950
256
128
64
32
16
8
4
2
1
M Count
M8
M7
M6
M5
M4
M3
M2
M1
M0
200
0
1
1
0
0
1
0
0
0
201
0
1
1
0
0
1
0
0
1
202
0
1
1
0
0
1
0
1
0
203
0
1
1
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
472
1
1
1
0
1
1
0
0
0
473
1
1
1
0
1
1
0
0
1
474
1
1
1
0
1
1
0
1
0
475
1
1
1
0
1
1
0
1
1
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the reference
oscillator is divided by eight before being sent to the phase
detector. With a 16MHz crystal, this provides a reference
frequency of 2MHz.
The VCO within the PLL operates over a range of 400–
950MHz. Its output is scaled by a divider that is configured by
either the serial or parallel interfaces. The output of this loop
divider is also applied to the phase detector.
The phase detector and loop filter force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M
(either too high or too low) the PLL will not achieve loop lock.
External loop filter components are utilized to allow for optimal
phase jitter performance.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. The
output divider is configured through either the serial or the
parallel interfaces and can provide one of four divider ratios
(1, 2, 4 or 8). This divider extends the performance of the part
while providing a 50% duty cycle.
The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated in 50Ω to VCC –2volts. The positive reference for
the output driver is provided by a dedicated power pin
(VCC_OUT) to reduce noise induced jitter.
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[8:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD input is held LOW
until sometime after power becomes valid. With S_LOAD
held LOW, on the LOW-to-HIGH transition of P_LOAD, the
parallel inputs are captured. The parallel interface has
priority over the serial interface. Internal pull-up resistors
are provided on the M[8:0] and N[1:0] inputs to reduce
component count.
The serial interface logic is implemented with a 14-bit shift
register scheme. The register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet set-up and
hold timing as specified in the AC parameters section of this
data sheet. With P_LOAD held HIGH, the configuration latches
will capture the value in the shift register on the HIGH-to-LOW
edge of the S_LOAD input. See the programming section for
more information.
The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.
4
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